.include "m8def.inc"



.def null          =r5
.def temp0         =r16
.def leds          =r17




;########
.CSEG
.org 0
rjmp RESET ; Reset Handler
reti; rjmp RESET ; Reset Handler
reti; rjmp EXT_INT0 ; IRQ0 Handler
reti; rjmp EXT_INT1 ; IRQ1 Handler
reti; rjmp TIM2_COMP ; Timer2 Compare Handler
reti; rjmp TIM2_OVF ; Timer2 Overflow Handler
reti; rjmp TIM1_CAPT ; Timer1 Capture Handler
reti; rjmp TIM1_COMPA ; Timer1 CompareA Handler
reti; rjmp TIM1_COMPB ; Timer1 CompareB Handler
reti; rjmp TIM1_OVF ; Timer1 Overflow Handler
reti; rjmp TIM0_OVF ; Timer0 Overflow Handler
reti; rjmp SPI_STC ; SPI Transfer Complete Handler
reti; rjmp USART_RXC ; USART RX Complete Handler
reti; rjmp USART_UDRE ; UDR Empty Handler
reti; rjmp USART_TXC ; USART TX Complete Handler
reti; rjmp ADC ; ADC Conversion Complete Handler
reti; rjmp EE_RDY ; EEPROM Ready Handler
reti; rjmp ANA_COMP ; Analog Comparator Handler
reti; rjmp TWSI ; Two-wire Serial Interface Handler
reti; rjmp SPM_RDY ; Store Program Memory Ready Handler
;########



RESET:
;###### init SATACK
ldi temp0,high(RAMEND) ; Main program start
out SPH,temp0 ; Set Stack Pointer to top of RAM
ldi temp0,low(RAMEND)
out SPL,temp0
;###############





ldi temp0,0b00000000 ; PORTC D7..D0
out DDRB, temp0

ldi temp0,0b00111100
out DDRC, temp0  ; Port B5..B2 = out, B7,B6,B1,B0 = in = in

ldi temp0,0b00000000
out DDRD, temp0  ; PORTD D7..D0 = in






clr null
ldi leds,0b00100000 ; set initial value




MAIN_LOOP:

rcall PAUSE_1_SEK

out PORTC,leds

rcall ROTATE

rcall PAUSE_1_SEK

out PORTC,null

rjmp MAIN_LOOP


;################################################
ROTATE:
push temp0
mov	temp0,leds	; âî âðåìåííûé
ror	temp0		; ðåçóëüòàò ïî áàðàáàíó, ãëàâíîå C áèò
ror	leds		; òóò â 0 âäâèíåòñß ñòàðøèé!
sbrc leds,1 ; skip if bit #0 is clr
ldi leds,0b00100000 ; set initial value
sbrc leds,6 ; skip if bit #6 is clr
ldi leds,0b00000100 ;
pop temp0
ret

;################################################
PAUSE_1_SEK:
push R17
push R18
push R19
; ============================= 
; ----------------------------- 
; delaying 3999996 cycles:
          ldi  R17, $24
WGLOOP0:  ldi  R18, $BC
WGLOOP1:  ldi  R19, $C4
WGLOOP2:  dec  R19
          brne WGLOOP2
          dec  R18
          brne WGLOOP1
          dec  R17
          brne WGLOOP0
; ----------------------------- 
; ============================= 
pop R19
pop R18
pop R17
ret