LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY test IS
END test;
 
ARCHITECTURE behavior OF test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT SHIFT_REGISTER_24_bit
    PORT(
         DATA : INOUT  std_logic_vector(0 to 7);
         CS : IN  std_logic;
         SH : IN  std_logic;
         IN_OUT : IN  std_logic;
         CLK : IN  std_logic;
         WR_RD : IN  std_logic;
         RL : IN  std_logic;
         PARITET : OUT  std_logic;
         ZER : OUT  std_logic;
         out_TR : OUT  std_logic_vector(0 to 9);
			stat	: OUT  STD_LOGIC_VECTOR (0 to 1)
        );
    END COMPONENT;
    

   --Inputs
   signal CS : std_logic := '1';
   signal SH : std_logic := '1';
   signal IN_OUT : std_logic := '0';
   signal CLK : std_logic := '1';
   signal WR_RD : std_logic := '1';
   signal RL : std_logic := '0';

	--BiDirs
   signal DATA : std_logic_vector(0 to 7);

 	--Outputs
   signal PARITET : std_logic;
   signal ZER : std_logic;
   signal out_TR : std_logic_vector(0 to 9);
	signal stat   : std_logic_vector(0 to 1);

   -- Clock period definitions
   constant CLK_period : time := 10 ns;
 
BEGIN


--RROC_CD : process
--begin
--CS <= 
--end process RROC_CD;

RROC_WR_RD : process
begin
WR_RD <= '1' , '1' after 10 ns, '1' after 20 ns, '1' after 30 ns,	'1' after 40 ns,
			'0' after 50 ns, '0' after 60 ns, '0' after 70 ns;
wait for 80 ns;			
end process;

RROC_SH : process
begin
SH <= '0' , '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '1' after 40 ns,
		'0' after 50 ns, '0' after 60 ns, '0' after 70 ns ;
		wait for 80 ns;
end process;
 
	-- Instantiate the Unit Under Test (UUT)
   uut: SHIFT_REGISTER_24_bit PORT MAP (
          DATA => DATA,
          CS => CS,
          SH => SH,
          IN_OUT => IN_OUT,
          CLK => CLK,
          WR_RD => WR_RD,
          RL => RL,
          PARITET => PARITET,
          ZER => ZER,
          out_TR => out_TR,
			 stat => stat
        );

   -- Clock process definitions
   CLK_process :process
	begin		
		CLK <= '0';
		wait for CLK_period/2;
		CLK <= '1';
		wait for CLK_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for CLK_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;