library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Декларация D триггера 

entity DFF is
port(
		CLK,D			: in  STD_LOGIC;
		Q				: out STD_LOGIC);
end DFF;

-- Описание архитектуры D триггера (срабатывающий по переднему фронту)

architecture Behavioral of DFF is
begin
process(CLK)
begin
if(CLK'event and CLK = '1') then
Q <= D;
end if;
end  process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Декларация защёлки

entity LATCH is
port(
		CLK,D			: in  STD_LOGIC;
		Q				: out STD_LOGIC);
end LATCH;

-- Описание архитектуры защёлки

architecture Behavioral of LATCH is
begin
process(CLK)
begin
if( CLK = '1' ) then
Q <= D;
end if;
end  process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Декларация 8 битного регистра

entity REGISTR_8_BIT is
port(
		D	 :	in	STD_LOGIC_VECTOR(0 to 7);
		CLK :	in	STD_LOGIC;
		OE	 : in STD_LOGIC;
		Q	 : out	STD_LOGIC_VECTOR(0 to 7)
	  );
end REGISTR_8_BIT;

-- Описание архитектуры 8 битного регистра 

architecture Behavioral of REGISTR_8_BIT is
component DFF
port (
		CLK,D : in  STD_LOGIC;
		Q		: out STD_LOGIC
		);
end	component;
begin
p0:process
begin
wait until OE = '1';
for i in 0 to 7 loop
Q(i) <= 'Z';
end	loop;
end	process;
g0 : for i in 0 to 7 generate
allbit : DFF 
port map( D => D(i), CLK => CLK, Q => Q(i));
end generate;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Описние интерфейса 8 битного развязывающего буфера

entity buffer_8_BIT is
port(
		D	 :	in	STD_LOGIC_VECTOR(0 to 7);
		CLK :	in	STD_LOGIC;
		OE	 : in STD_LOGIC;
		Q	 : out	STD_LOGIC_VECTOR(0 to 7)
	  );
end buffer_8_BIT;

-- Описние архтектуры 8 битного развязывающего буфера

architecture Behavioral of buffer_8_BIT is
component LATCH
port (
		CLK,D : in  STD_LOGIC;
		Q		: out STD_LOGIC
		);
end	component;
begin

p0:process
begin
wait until OE = '1';
for i in 0 to 7 loop
Q(i) <= 'Z';
end	loop;
end	process;
g0 : for i in 0 to 7 generate
allbit : LATCH 
port map( D => D(i), CLK => CLK, Q => Q(i));

end generate;
end 	Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Описние интерфейса дешифратора

entity decoder is
port(
			 A,B,C : in	STD_LOGIC;
			 Y		 : out STD_LOGIC_VECTOR (0 to 7)
	  );
end 	decoder;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Описние архитектуры дешифратора  

architecture Behavioral of decoder is
-- Объявлние и опрделение функции AND_NOT
function ANDNOT( x1,x2,x3 : STD_LOGIC) 
return	 STD_LOGIC is
variable y : STD_LOGIC;
begin
y := not (x1 and x2 and x3 );
return y;
end ANDNOT;
begin
y(0) <= ANDNOT( not A, not B, not C);
y(1) <= ANDNOT(     A, not B, not C);
y(2) <= ANDNOT( not A,     B, not C);
y(3) <= ANDNOT(     A,     B, not C);
y(4) <= ANDNOT( not A, not B,     C);
y(5) <= ANDNOT(     A, not B,     C);
y(6) <= ANDNOT( not A,     B,     C);
y(7) <= ANDNOT(     A,     B,     C);
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Описние интерфейса контроллера паритета

entity parity_checkers is
port(
		A  				  : in STD_LOGIC_VECTOR;
		EVEN,ODD			  : in STD_LOGIC;
		SUM_EVEN,SUM_ODD : out STD_LOGIC
	  );
end parity_checkers;	  

-- Описние архитектуры контроллера паритета

architecture Behavioral of parity_checkers is

function XORFUN(x1,x2,x3,x4 : STD_LOGIC ) 
return STD_LOGIC is
variable y : STD_LOGIC;
begin
y := ( not ( x1 xor x2 ) ) xor ( not ( x3 xor x4 ) );
return y;
end XORFUN;

function OUTPUT(x1,x2,x3,x4 : STD_LOGIC )
return STD_LOGIC is
variable y : STD_LOGIC;
begin
y :=  not ( (x1 and x2) or ( x3 and x4 ) ); 
return y;
end OUTPUT;

signal R1 : STD_LOGIC;
begin 
R1 <= not ( XORFUN(A(0),A(1),A(2),A(3)) xor XORFUN(A(4),A(5),A(6),A(7)));
SUM_EVEN <= OUTPUT( R1,ODD,not R1,EVEN);
SUM_ODD  <= OUTPUT( R1,EVEN,not R1,ODD);

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Описние интерфейса проекта

entity SHIFT_REGISTER_24_bit is
    Port ( DATA 	: inout  STD_LOGIC_VECTOR (0 to 7);
           CS 		: in  STD_LOGIC;
           SH 		: in  STD_LOGIC;
           IN_OUT : in  STD_LOGIC;
           CLK 	: in  STD_LOGIC;
           WR_RD 	: in  STD_LOGIC;
           RL 		: in  STD_LOGIC;
			  PARITET: out STD_LOGIC;
			  ZER		: out STD_LOGIC;
			  out_TR : out STD_LOGIC_VECTOR (0 to 9);
			  stat	: out  STD_LOGIC_VECTOR (0 to 1)
			);
end SHIFT_REGISTER_24_bit;

-- Описние архитектуры проекта

architecture Behavioral of SHIFT_REGISTER_24_bit is
-- объявляем компоненты в архитектуре главного объекта
component DFF
port(
		CLK,D			: in  STD_LOGIC;
		Q				: out STD_LOGIC);
end component;

component LATCH
port(
		CLK,D			: in  STD_LOGIC;
		Q				: out STD_LOGIC);
end component;

component REGISTR_8_BIT
port(
		D	 :	in	STD_LOGIC_VECTOR(0 to 7);
		CLK :	in	STD_LOGIC;
		OE	 : in STD_LOGIC;
		Q	 : out	STD_LOGIC_VECTOR(0 to 7)
	  );
end component;

component buffer_8_BIT
port(
		D	 :	in	STD_LOGIC_VECTOR(0 to 7);
		CLK :	in	STD_LOGIC;
		OE	 : in STD_LOGIC;
		Q	 : out	STD_LOGIC_VECTOR(0 to 7)
	  );
end component;

component parity_checkers
port(
		A  				  : in STD_LOGIC_VECTOR;
		EVEN,ODD			  : in STD_LOGIC;
		SUM_EVEN,SUM_ODD : out STD_LOGIC
	  );	
end component;	 

component decoder
port(
			 A,B,C : in	STD_LOGIC;
			 Y		 : out STD_LOGIC_VECTOR (0 to 7)
	  );
end component;	 

-- выходные линии с буферов ( 4 штук по 8 бит)
signal lineBUFQ4 : STD_LOGIC_VECTOR ( 0 to 7);
--выходные линии со сдвиговых регистров
signal lineREG1 : STD_LOGIC_VECTOR ( 0 to 7);
signal lineREG2 : STD_LOGIC_VECTOR ( 0 to 7);
signal lineREG3 : STD_LOGIC_VECTOR ( 0 to 7);
--управляющие линии с автомата
signal line_avtomat_control : STD_LOGIC_VECTOR ( 0 to 9);
-- линии управления буферами с декодера
signal lineDEC : STD_LOGIC_VECTOR ( 0 to 7);
-- линии из порта SUM_ODD , контроллера нечётности
signal line_paritet : STD_LOGIC;
-- линии из схемы контроля чётности (триггеров)
signal line_trigger : STD_LOGIC_VECTOR ( 0 to 2);
-- линии функции возбуждения памяти (триггеров)
signal exсit_fun_line : STD_LOGIC_VECTOR ( 0 to 1) := "01";
-- линия текущего состояния памяти (триггеров)
signal state_line : STD_LOGIC_VECTOR ( 0 to 1) := "01";

begin

-- объявляем буфера и показываем входные и выходные связи

BUF1 : buffer_8_BIT 
port map( D => DATA, CLK => CLK, OE => lineDEC(0),Q => lineREG1);
BUF2 : buffer_8_BIT 
port map( D => DATA, CLK => CLK, OE => lineDEC(1),Q => lineREG2);
BUF3 : buffer_8_BIT 
port map( D => DATA, CLK => CLK, OE => lineDEC(2),Q => lineREG3);

BUF4 : buffer_8_BIT 
port map( D(0) => lineREG3(7),D(1) => lineREG1(0),D(2) => lineREG1(1),D(3) => lineREG1(2),
		    D(4) => lineREG1(3),D(5) => lineREG1(4),D(6) => lineREG1(5),D(7) => lineREG1(6),
			 CLK => CLK, OE => lineDEC(3),Q => lineBUFQ4);
BUF5 : buffer_8_BIT 
port map( D(0) => lineREG1(7),D(1) => lineREG2(0),D(2) => lineREG2(1),D(3) => lineREG2(2),
		    D(4) => lineREG2(3),D(5) => lineREG2(4),D(6) => lineREG2(5),D(7) => lineREG2(6),
			 CLK => CLK, OE => lineDEC(4),Q => lineBUFQ4);
BUF6 : buffer_8_BIT 
port map( D(0) => lineREG2(7),D(1) => lineREG3(0),D(2) => lineREG3(1),D(3) => lineREG3(2),
		    D(4) => lineREG3(3),D(5) => lineREG3(4),D(6) => lineREG3(5),D(7) => lineREG3(6),
			 CLK => CLK, OE => lineDEC(5),Q => lineBUFQ4);
			 
BUF7 : buffer_8_BIT 
port map( D => lineBUFQ4, CLK => CLK, OE => line_avtomat_control(9),Q => DATA);

-- объявляем регистры  и показываем входные и выходные связи

REG1 : REGISTR_8_BIT
port map( D(0) => lineREG1(0),D(1) => lineREG1(1), D(2) => lineREG1(2), D(3) => lineREG1(3), 
          D(4) => lineREG1(4),D(5) => lineREG1(5), D(6) => lineREG1(6), D(7) => lineREG1(7),  
			 CLK  => CLK, OE => line_avtomat_control(3),
			 Q(0) => lineREG3(7),Q(1) => lineREG1(0),Q(2)  => lineREG1(1),Q(3)  => lineREG1(2),
			 Q(4) => lineREG1(3),Q(5) => lineREG1(4),Q(6)  => lineREG1(5),Q(7)  => lineREG1(6)	);
			 
REG2 : REGISTR_8_BIT
port map( D(0) => lineREG2(0),D(1) => lineREG2(1), D(2) => lineREG2(2), D(3) => lineREG2(3), 
          D(4) => lineREG2(4),D(5) => lineREG2(5), D(6) => lineREG2(6), D(7) => lineREG2(7),  
			 CLK  => CLK, OE => line_avtomat_control(2),
			 Q(0) => lineREG1(7),Q(1) => lineREG2(0),Q(2)  => lineREG2(1),Q(3)  => lineREG2(2),
			 Q(4) => lineREG2(3),Q(5) => lineREG2(4),Q(6)  => lineREG2(5),Q(7)  => lineREG2(6)	);
			 
REG3 : REGISTR_8_BIT
port map( D(0) => lineREG3(0),D(1) => lineREG3(1), D(2) => lineREG3(2), D(3) => lineREG3(3), 
          D(4) => lineREG3(4),D(5) => lineREG3(5), D(6) => lineREG3(6), D(7) => lineREG3(7),  
			 CLK  => CLK, OE => line_avtomat_control(1),
			 Q(0) => lineREG2(7),Q(1) => lineREG3(0),Q(2)  => lineREG3(1),Q(3)  => lineREG3(2),
			 Q(4) => lineREG3(3),Q(5) => lineREG3(4),Q(6)  => lineREG3(5),Q(7)  => lineREG3(6)	);
			 
PARIT : parity_checkers	
port map( A => lineBUFQ4,EVEN => '0',ODD => '1',SUM_EVEN => open  ,SUM_ODD => line_paritet );
			 
DEC : decoder
port map( A => line_avtomat_control(9), B => line_avtomat_control(8), C => line_avtomat_control(7), Y => lineDEC );

PARIT_TRIG1 : LATCH
port map( CLK => not lineDEC(3), D => line_paritet, Q => line_trigger(0));
PARIT_TRIG2 : LATCH
port map( CLK => not lineDEC(4), D => line_paritet, Q => line_trigger(1));
PARIT_TRIG3 : LATCH
port map( CLK => not lineDEC(5), D => line_paritet, Q => line_trigger(2));
	
TRIG1_AVT : DFF
port map( CLK => CLK,D => exсit_fun_line(0),Q => state_line(0));
TRIG2_AVT : DFF
port map( CLK => CLK,D => exсit_fun_line(1),Q => state_line(1));

START : process
begin




-- функции возбуждения памяти (триггеров)

exсit_fun_line(0) <= ( (state_line(0) and not CS ) or ( state_line(0) and not WR_RD and not SH ) or 
							( state_line(1) and state_line(0) and not SH ) or ( state_line(1) and not WR_RD and 
							not SH and CS ) );
							
exсit_fun_line(1) <= (state_line(1) and not CS ) or ( not state_line(1)and not WR_RD and not SH and CS ) or	
                     (state_line(0) and not WR_RD and not SH and CS) or (not state_line(1) and not state_line(0) and 
 						    WR_RD and CS)  ;
						 
stat	<= state_line;	


						 
--функции возбуждения выходов 

line_avtomat_control(9) <= ( not CS or ( not WR_RD and not SH ) or ( WR_RD and SH ) or ( not state_line(1) and
									not state_line(0) and WR_RD ) or ( state_line(1) and state_line(0) and WR_RD ) );
									
line_avtomat_control(8) <= ( not CS or ( state_line(1) and WR_RD ) or ( WR_RD and SH ) or ( state_line(1) and
										state_line(0) and not SH ) or ( not state_line(1) and not state_line(0) and not	
										WR_RD and not SH) or ( state_line(1) and WR_RD ) );
										
line_avtomat_control(7) <= ( not CS or ( WR_RD and SH ) or ( state_line(1) and state_line(0) and WR_RD ) or
									( state_line(0) and not WR_RD and not SH ) );

line_avtomat_control(6) <= ( not CS or ( WR_RD and not SH ) or ( state_line(0) and not SH ) or ( state_line(1) 
									and not SH) );		

line_avtomat_control(5) <= ( not CS or ( WR_RD and not SH ) or ( state_line(0) and not SH ) or (not state_line(1) 
									and  not SH));			

line_avtomat_control(4) <=  ( not CS  or ( WR_RD and not SH ) or ( not state_line(0) and not state_line(1) and not SH )
									or ( state_line(1) and not SH ) );
	
line_avtomat_control(3) <=  ( ( not state_line(0) and not WR_RD and not SH and CS ) or ( not state_line(1) and WR_RD and
									SH and CS ) or ( state_line(0) and WR_RD and SH and CS ) or ( not state_line(1) and 
									state_line(0) and not SH and CS ) );

line_avtomat_control(2) <= ( ( not state_line(1) and not WR_RD and not SH and CS) or ( not state_line(1) and WR_RD and 
									SH and CS ) or ( not state_line(1) and not state_line(0) and WR_RD and CS ) or ( state_line(0)
									and WR_RD and SH and CS ) or (state_line(1) and not state_line(0) and not WR_RD and not SH
									and CS ) );

line_avtomat_control(1) <= ( (state_line(1) and not state_line(0) and not SH and CS ) or ( not state_line(1) and not WR_RD
									and not SH and CS) or ( not state_line(1) and WR_RD and SH and CS ) or ( state_line(0) and WR_RD
									and SH and CS) );

line_avtomat_control(0) <= ( WR_RD or (not CS ) or ( state_line(1) and state_line(0) and not SH ));


wait for 10 ns;

PARITET	<= ( line_trigger(0) xor line_trigger(1) xor line_trigger(2) );

OUT_TR  <= line_avtomat_control;



end process;

end Behavioral;