#asm
_w1_init:
    push r30
_w1_init_0:

    ldi r30,0
    cpse R5,R30
    jmp _w1_init_1
    
    pop r30
    clr  r30
    cbi  __w1_port,__w1_bit_0
    sbi  __w1_port-1,__w1_bit_0
    __DELAY_USW 0x1E0
    cbi  __w1_port-1,__w1_bit_0
    __DELAY_USB 0x13
    sbis __w1_port-2,__w1_bit_0
    ret
    __DELAY_USB 0x65
    sbis __w1_port-2,__w1_bit_0
    inc  r30
    __DELAY_USW 0x186
    ret
_w1_init_1:

    ldi r30,1
    cpse R5,R30
    jmp _w1_init_2
    
    pop r30
    clr  r30
    cbi  __w1_port,__w1_bit_1
    sbi  __w1_port-1,__w1_bit_1
    __DELAY_USW 0x1E0
    cbi  __w1_port-1,__w1_bit_1
    __DELAY_USB 0x13
    sbis __w1_port-2,__w1_bit_1
    ret
    __DELAY_USB 0x65
    sbis __w1_port-2,__w1_bit_1
    inc  r30
    __DELAY_USW 0x186
    ret
_w1_init_2:

    ldi r30,2
    cpse R5,R30
    jmp _w1_init_3
    
    pop r30
    clr  r30
    cbi  __w1_port,__w1_bit_2
    sbi  __w1_port-1,__w1_bit_2
    __DELAY_USW 0x1E0
    cbi  __w1_port-1,__w1_bit_2
    __DELAY_USB 0x13
    sbis __w1_port-2,__w1_bit_2
    ret
    __DELAY_USB 0x65
    sbis __w1_port-2,__w1_bit_2
    inc  r30
    __DELAY_USW 0x186
    ret
_w1_init_3:

    ldi r30,3
    cpse R5,R30
    jmp _w1_init_4
    
    pop r30
    clr  r30
    cbi  __w1_port,__w1_bit_3
    sbi  __w1_port-1,__w1_bit_3
    __DELAY_USW 0x1E0
    cbi  __w1_port-1,__w1_bit_3
    __DELAY_USB 0x13
    sbis __w1_port-2,__w1_bit_3
    ret
    __DELAY_USB 0x65
    sbis __w1_port-2,__w1_bit_3
    inc  r30
    __DELAY_USW 0x186
    ret    
_w1_init_4:

    ldi r30,4
    cpse R5,R30
    jmp _w1_init_5
    
    pop r30
    clr  r30
    cbi  __w1_port,__w1_bit_4
    sbi  __w1_port-1,__w1_bit_4
    __DELAY_USW 0x1E0
    cbi  __w1_port-1,__w1_bit_4
    __DELAY_USB 0x13
    sbis __w1_port-2,__w1_bit_4
    ret
    __DELAY_USB 0x65
    sbis __w1_port-2,__w1_bit_4
    inc  r30
    __DELAY_USW 0x186
    ret
_w1_init_5:

    ldi r30,5
    cpse R5,R30
    jmp _w1_init_6
    
    pop r30
    clr  r30
    cbi  __w1_port,__w1_bit_5
    sbi  __w1_port-1,__w1_bit_5
    __DELAY_USW 0x1E0
    cbi  __w1_port-1,__w1_bit_5
    __DELAY_USB 0x13
    sbis __w1_port-2,__w1_bit_5
    ret
    __DELAY_USB 0x65
    sbis __w1_port-2,__w1_bit_5
    inc  r30
    __DELAY_USW 0x186
    ret
_w1_init_6:

    ldi r30,6
    cpse R5,R30
    jmp _w1_init_7
    
    pop r30
    clr  r30
    cbi  __w1_port,__w1_bit_6
    sbi  __w1_port-1,__w1_bit_6
    __DELAY_USW 0x1E0
    cbi  __w1_port-1,__w1_bit_6
    __DELAY_USB 0x13
    sbis __w1_port-2,__w1_bit_6
    ret
    __DELAY_USB 0x65
    sbis __w1_port-2,__w1_bit_6
    inc  r30
    __DELAY_USW 0x186
    ret
_w1_init_7:
   pop r30 
    clr  r30
    cbi  __w1_port,__w1_bit_7
    sbi  __w1_port-1,__w1_bit_7
    __DELAY_USW 0x1E0
    cbi  __w1_port-1,__w1_bit_7
    __DELAY_USB 0x13
    sbis __w1_port-2,__w1_bit_7
    ret
    __DELAY_USB 0x65
    sbis __w1_port-2,__w1_bit_7
    inc  r30
    __DELAY_USW 0x186
    ret

__w1_read_bit:
    push r30
__w1_read_bit_0:

    ldi r30,0
    cpse R5,R30
    jmp __w1_read_bit_1
            
    pop r30
    sbi  __w1_port-1,__w1_bit_0
    __DELAY_USB 0x3
    cbi  __w1_port-1,__w1_bit_0
    __DELAY_USB 0xF
    clc
    sbic __w1_port-2,__w1_bit_0
    sec
    ror  r30
    __DELAY_USB 0x6B
    ret
__w1_read_bit_1:

    ldi r30,1
    cpse R5,R30
    jmp __w1_read_bit_2
    
    pop r30
    sbi  __w1_port-1,__w1_bit_1
    __DELAY_USB 0x3
    cbi  __w1_port-1,__w1_bit_1
    __DELAY_USB 0xF
    clc
    sbic __w1_port-2,__w1_bit_1
    sec
    ror  r30
    __DELAY_USB 0x6B
    ret
__w1_read_bit_2:

    ldi r30,2
    cpse R5,R30
    jmp __w1_read_bit_3
           
    pop r30
    sbi  __w1_port-1,__w1_bit_2
    __DELAY_USB 0x3
    cbi  __w1_port-1,__w1_bit_2
    __DELAY_USB 0xF
    clc
    sbic __w1_port-2,__w1_bit_2
    sec
    ror  r30
    __DELAY_USB 0x6B
    ret
__w1_read_bit_3:

    ldi r30,3
    cpse R5,R30
    jmp __w1_read_bit_4
           
    pop r30
    sbi  __w1_port-1,__w1_bit_3
    __DELAY_USB 0x3
    cbi  __w1_port-1,__w1_bit_3
    __DELAY_USB 0xF
    clc
    sbic __w1_port-2,__w1_bit_3
    sec
    ror  r30
    __DELAY_USB 0x6B
    ret
__w1_read_bit_4:

    ldi r30,4
    cpse R5,R30
    jmp __w1_read_bit_5
           
    pop r30
    sbi  __w1_port-1,__w1_bit_4
    __DELAY_USB 0x3
    cbi  __w1_port-1,__w1_bit_4
    __DELAY_USB 0xF
    clc
    sbic __w1_port-2,__w1_bit_4
    sec
    ror  r30
    __DELAY_USB 0x6B
    ret
__w1_read_bit_5:

    ldi r30,5
    cpse R5,R30
    jmp __w1_read_bit_6
           
    pop r30
    sbi  __w1_port-1,__w1_bit_5
    __DELAY_USB 0x3
    cbi  __w1_port-1,__w1_bit_5
    __DELAY_USB 0xF
    clc
    sbic __w1_port-2,__w1_bit_5
    sec
    ror  r30
    __DELAY_USB 0x6B
    ret
__w1_read_bit_6:

    ldi r30,6
    cpse R5,R30
    jmp __w1_read_bit_7
           
    pop r30
    sbi  __w1_port-1,__w1_bit_6
    __DELAY_USB 0x3
    cbi  __w1_port-1,__w1_bit_6
    __DELAY_USB 0xF
    clc
    sbic __w1_port-2,__w1_bit_6
    sec
    ror  r30
    __DELAY_USB 0x6B
    ret
__w1_read_bit_7:
    pop r30
    sbi  __w1_port-1,__w1_bit_7
    __DELAY_USB 0x3
    cbi  __w1_port-1,__w1_bit_7
    __DELAY_USB 0xF
    clc
    sbic __w1_port-2,__w1_bit_7
    sec
    ror  r30
    __DELAY_USB 0x6B
    ret

__w1_write_bit:
    push r30
__w1_write_bit_0:

    ldi r30,0
    cpse R5,R30
    jmp __w1_write_bit_1
            
    pop r30
    clt
    sbi  __w1_port-1,__w1_bit_0
    __DELAY_USB 0x3
    sbrc r23,0
    cbi  __w1_port-1,__w1_bit_0
    __DELAY_USB 0x11
    sbic __w1_port-2,__w1_bit_0
    rjmp __w1_write_bit0
    sbrs r23,0
    rjmp __w1_write_bit1
    ret
__w1_write_bit_1:

    ldi r30,1
    cpse R5,R30
    jmp __w1_write_bit_2

    pop r30
    clt
    sbi  __w1_port-1,__w1_bit_1
    __DELAY_USB 0x3
    sbrc r23,0
    cbi  __w1_port-1,__w1_bit_1
    __DELAY_USB 0x11
    sbic __w1_port-2,__w1_bit_1
    rjmp __w1_write_bit0
    sbrs r23,0
    rjmp __w1_write_bit1
    ret
__w1_write_bit_2:

    ldi r30,2
    cpse R5,R30
    jmp __w1_write_bit_3

    pop r30
    clt
    sbi  __w1_port-1,__w1_bit_2
    __DELAY_USB 0x3
    sbrc r23,0
    cbi  __w1_port-1,__w1_bit_2
    __DELAY_USB 0x11
    sbic __w1_port-2,__w1_bit_2
    rjmp __w1_write_bit0
    sbrs r23,0
    rjmp __w1_write_bit1
    ret
__w1_write_bit_3:

    ldi r30,3
    cpse R5,R30
    jmp __w1_write_bit_4
    
    pop r30
    clt
    sbi  __w1_port-1,__w1_bit_3
    __DELAY_USB 0x3
    sbrc r23,0
    cbi  __w1_port-1,__w1_bit_3
    __DELAY_USB 0x11
    sbic __w1_port-2,__w1_bit_3
    rjmp __w1_write_bit0
    sbrs r23,0
    rjmp __w1_write_bit1
    ret
__w1_write_bit_4:

    ldi r30,4
    cpse R5,R30
    jmp __w1_write_bit_5

    pop r30
    clt
    sbi  __w1_port-1,__w1_bit_4
    __DELAY_USB 0x3
    sbrc r23,0
    cbi  __w1_port-1,__w1_bit_4
    __DELAY_USB 0x11
    sbic __w1_port-2,__w1_bit_4
    rjmp __w1_write_bit0
    sbrs r23,0
    rjmp __w1_write_bit1
    ret
__w1_write_bit_5:

    ldi r30,5
    cpse R5,R30
    jmp __w1_write_bit_6
          
    pop r30
    clt
    sbi  __w1_port-1,__w1_bit_5
    __DELAY_USB 0x3
    sbrc r23,0
    cbi  __w1_port-1,__w1_bit_5
    __DELAY_USB 0x11
    sbic __w1_port-2,__w1_bit_5
    rjmp __w1_write_bit0
    sbrs r23,0
    rjmp __w1_write_bit1
    ret
__w1_write_bit_6:

    ldi r30,6
    cpse R5,R30
    jmp __w1_write_bit_7
    
    pop r30
    clt
    sbi  __w1_port-1,__w1_bit_6
    __DELAY_USB 0x3
    sbrc r23,0
    cbi  __w1_port-1,__w1_bit_6
    __DELAY_USB 0x11
    sbic __w1_port-2,__w1_bit_6
    rjmp __w1_write_bit0
    sbrs r23,0
    rjmp __w1_write_bit1
    ret
__w1_write_bit_7:

    pop r30
    clt
    sbi  __w1_port-1,__w1_bit_7
    __DELAY_USB 0x3
    sbrc r23,0
    cbi  __w1_port-1,__w1_bit_7
    __DELAY_USB 0x11
    sbic __w1_port-2,__w1_bit_7
    rjmp __w1_write_bit0
    sbrs r23,0
    rjmp __w1_write_bit1
    ret
__w1_write_bit0:
    sbrs r23,0
    ret
__w1_write_bit1:
    push r30
__w1_write_bit1_0:

    ldi r30,0
    cpse R5,R30
    jmp __w1_write_bit1_1
    
    pop r30
    __DELAY_USB 0x64
    cbi  __w1_port-1,__w1_bit_0
    __DELAY_USB 0x7
    set
    ret
__w1_write_bit1_1:

    ldi r30,1
    cpse R5,R30
    jmp __w1_write_bit1_2
    
    pop r30
    __DELAY_USB 0x64
    cbi  __w1_port-1,__w1_bit_1
    __DELAY_USB 0x7
    set
    ret
__w1_write_bit1_2:

    ldi r30,2
    cpse R5,R30
    jmp __w1_write_bit1_3
           
    pop r30
    __DELAY_USB 0x64
    cbi  __w1_port-1,__w1_bit_2
    __DELAY_USB 0x7
    set
    ret
__w1_write_bit1_3:

    ldi r30,3
    cpse R5,R30
    jmp __w1_write_bit1_4
           
    pop r30
    __DELAY_USB 0x64
    cbi  __w1_port-1,__w1_bit_3
    __DELAY_USB 0x7
    set
    ret
__w1_write_bit1_4:

    ldi r30,4
    cpse R5,R30
    jmp __w1_write_bit1_5
           
    pop r30
    __DELAY_USB 0x64
    cbi  __w1_port-1,__w1_bit_4
    __DELAY_USB 0x7
    set
    ret 
__w1_write_bit1_5:

    ldi r30,5
    cpse R5,R30
    jmp __w1_write_bit1_6
           
    pop r30
    __DELAY_USB 0x64
    cbi  __w1_port-1,__w1_bit_5
    __DELAY_USB 0x7
    set
    ret 
__w1_write_bit1_6:

    ldi r30,6
    cpse R5,R30
    jmp __w1_write_bit1_7
           
    pop r30
    __DELAY_USB 0x64
    cbi  __w1_port-1,__w1_bit_6
    __DELAY_USB 0x7
    set
    ret
__w1_write_bit1_7:

    pop r30
    __DELAY_USB 0x64
    cbi  __w1_port-1,__w1_bit_7
    __DELAY_USB 0x7
    set
    ret