| Schem_pwm Project Status (08/02/2013 - 22:11:04) | |||
| Project File: | pwm.xise | Parser Errors: | No Errors |
| Module Name: | Schem_pwm | Implementation State: | Synthesized |
| Target Device: | xc3s700a-4fg484 |
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No Errors |
| Product Version: | ISE 14.4 |
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No Warnings |
| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: | System Settings |
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| Device Utilization Summary (estimated values) | [-] | |||
| Logic Utilization | Used | Available | Utilization | |
| Number of Slices | 9 | 5888 | 0% | |
| Number of Slice Flip Flops | 9 | 11776 | 0% | |
| Number of 4 input LUTs | 17 | 11776 | 0% | |
| Number of bonded IOBs | 10 | 372 | 2% | |
| Number of GCLKs | 1 | 24 | 4% | |
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Ïò 2. àâã 22:11:03 2013 | 0 | 0 | 0 | |
| Translation Report | ||||||
| Map Report | ||||||
| Place and Route Report | ||||||
| Power Report | ||||||
| Post-PAR Static Timing Report | ||||||
| Bitgen Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Current | Ïò 2. àâã 22:16:09 2013 | |