[SETTINGS]
UUT_module%hellmachine%
TB_module%hellmachine_tb%
DSN_PATH%$DSN\src\TestBench%
OUTPUT_DIRECTORY%C:\My_Designs\test_spi\test_spi\src\TestBench%
STIMULUS%NO%
VECTORS_FILE%%
AWF_FILE%%
TB_FILE%hellmachine_TB.v%
MACRO_FILE%hellmachine_TB_runtest.do%
UUT_module_FILE%test_spi/compile/hellmachine.v%
LIBRARY_NAME%test_spi%
LIBRARY_TYPE%work%
TestBench_TYPE%simple%
ENABLE_FILE%none%
RESULT_FILE%none%

[GENERICS]

[PORTS]
A%in%[4:0]wire%NO%NOCLK%
CLKDAC%out%reg%NO%NOCLK%
CS%in%wire%NO%NOCLK%
DATAOUT%out%reg%NO%NOCLK%
DAT%inout%[7:0]tri%NO%NOCLK%
IOR%in%wire%NO%NOCLK%
IOW%in%wire%NO%NOCLK%
LTCH%out%[3:0]reg%NO%NOCLK%
MOSI%in%wire%NO%NOCLK%
RES%in%wire%NO%NOCLK%
SCK%in%wire%NO%NOCLK%

[SDF]

[INCLUDE]
[Verilog_FILES]
$DSN\compile\hellmachine.v

