#define PORTA PORT->Group[0] #define PORTB PORT->Group[1] #define PORTC PORT->Group[2] #define PMUXEN_bp 0 #define PMUXEN_bm (1 << PMUXEN_bp) #define PMUXE_pos 0 #define PMUXE_A (0x00 << PMUXE_pos) #define PMUXE_B (0x01 << PMUXE_pos) #define PMUXE_C (0x02 << PMUXE_pos) #define PMUXE_D (0x03 << PMUXE_pos) #define PMUXE_E (0x04 << PMUXE_pos) #define PMUXE_F (0x05 << PMUXE_pos) #define PMUXE_G (0x06 << PMUXE_pos) #define PMUXE_H (0x07 << PMUXE_pos) #define PMUXO_pos 4 #define PMUXO_A (0x00 << PMUXO_pos) #define PMUXO_B (0x01 << PMUXO_pos) #define PMUXO_C (0x02 << PMUXO_pos) #define PMUXO_D (0x03 << PMUXO_pos) #define PMUXO_E (0x04 << PMUXO_pos) #define PMUXO_F (0x05 << PMUXO_pos) #define PMUXO_G (0x06 << PMUXO_pos) #define PMUXO_H (0x07 << PMUXO_pos) //Register OSC8M (in SYSCTRL register) - 8MHz Internal Oscillator (OSC8M) Control #define OSC8M_FRANGE_pos 30 #define OSC8M_FRANGE_4_6MHz_bg (0x00 << OSC8M_FRANGE_pos) #define OSC8M_FRANGE_6_8MHz_bg (0x01 << OSC8M_FRANGE_pos) #define OSC8M_FRANGE_8_11MHz_bg (0x02 << OSC8M_FRANGE_pos) #define OSC8M_FRANGE_11_15MHz_bg (0x03 << OSC8M_FRANGE_pos) //OSC8M[29:28] - reserved #define OSC8M_CALIB_pos 16 #define OSC8M_CALIB_msk (0xFFFFFF << OSC8M_CALIB_pos) //OSC8M[15:10] - reserved #define OSC8M_PRESC_pos 8 #define OSC8M_PRESC_msk (0x03 << OSC8M_PRESC_pos) #define OSC8M_PRESC_8MHz_bg (0x00 << OSC8M_PRESC_pos) #define OSC8M_PRESC_4MHz_bg (0x01 << OSC8M_PRESC_pos) #define OSC8M_PRESC_2MHz_bg (0x02 << OSC8M_PRESC_pos) #define OSC8M_PRESC_1MHz_bg (0x03 << OSC8M_PRESC_pos) #define OSC8M_ONDEMAND_bp 7 #define OSC8M_ONDEMAND_bm (1 << OSC8M_ONDEMAND_bp) #define OSC8M_RUNSTDBY_bp 6 #define OSC8M_RUNSTDBY_bm (1 << OSC8M_RUNSTDBY_bp) //OSC8M[5:2] - reserved #define OSC8M_ENABLE_bp 1 #define OSC8M_ENABLE_bm (1 << OSC8M_ENABLE_bp) //OSC8M[0] - reserved //Register CTRL - Generic Clock Generator STATUS //CTRL[7:1] #define CTRL_SWRST_bp 0 #define CTRL_SWRST_bm (1 << CTRL_SWRST_bp) //Register STATUS - Generic Clock Generator STATUS #define STATUS_SYNCBUSY_bp 7 #define STATUS_SYNCBUSY_bm (1 << STATUS_SYNCBUSY_bp) //STATUS[6:0] //Register GENDIV - Generic Clock Generator Division //GENDIV[31:24] - reserved #define GENDIV_DIV_pos 8 #define GENDIV_DIV_msk (0xFFFF << GENDIV_DIV_pos) //GENDIV[7:4] - reserved #define GENDIV_GCG_ID_pos 0 #define GENDIV_GCG_ID_msk (0x0F << GENDIV_GCG_ID_pos) #define GENDIV_GCG_GEN0_bg (0x00 << GENDIV_GCG_ID_pos) #define GENDIV_GCG_GEN1_bg (0x01 << GENDIV_GCG_ID_pos) #define GENDIV_GCG_GEN2_bg (0x02 << GENDIV_GCG_ID_pos) #define GENDIV_GCG_GEN3_bg (0x03 << GENDIV_GCG_ID_pos) #define GENDIV_GCG_GEN4_bg (0x04 << GENDIV_GCG_ID_pos) #define GENDIV_GCG_GEN5_bg (0x05 << GENDIV_GCG_ID_pos) #define GENDIV_GCG_GEN6_bg (0x06 << GENDIV_GCG_ID_pos) #define GENDIV_GCG_GEN7_bg (0x07 << GENDIV_GCG_ID_pos) //Register CLKCTRL - Generic Clock Control register #define CLKCTRL_WRTLOCK_bp 15 #define CLKCTRL_WRTLOCK_bm (1 << CLKCTRL_WRTLOCK_bp) #define CLKCTRL_CLKEN_bp 14 #define CLKCTRL_CLKEN_bm (1 << CLKCTRL_CLKEN_bp) //CLKCTRL[13:12] - reserved #define CLKCTRL_GEN_pos 8 #define CLKCTRL_GEN0_bg (0x00 << CLKCTRL_GEN_pos) #define CLKCTRL_GEN1_bg (0x01 << CLKCTRL_GEN_pos) #define CLKCTRL_GEN2_bg (0x02 << CLKCTRL_GEN_pos) #define CLKCTRL_GEN3_bg (0x03 << CLKCTRL_GEN_pos) #define CLKCTRL_GEN4_bg (0x04 << CLKCTRL_GEN_pos) #define CLKCTRL_GEN5_bg (0x05 << CLKCTRL_GEN_pos) #define CLKCTRL_GEN6_bg (0x06 << CLKCTRL_GEN_pos) #define CLKCTRL_GEN7_bg (0x07 << CLKCTRL_GEN_pos) //CLKCTRL[7:6] - reserved #define CLKCTRL_ID_pos 0 #define CLKCTRL_DFLL48M_ref_bg (0x00 << CLKCTRL_ID_pos) #define CLKCTRL_WDT_bg (0x01 << CLKCTRL_ID_pos) #define CLKCTRL_RTC_bg (0x02 << CLKCTRL_ID_pos) #define CLKCTRL_EIC_bg (0x03 << CLKCTRL_ID_pos) #define CLKCTRL_EVSYS_CH0_bg (0x04 << CLKCTRL_ID_pos) #define CLKCTRL_EVSYS_CH1_bg (0x05 << CLKCTRL_ID_pos) #define CLKCTRL_EVSYS_CH2_bg (0x06 << CLKCTRL_ID_pos) #define CLKCTRL_EVSYS_CH3_bg (0x07 << CLKCTRL_ID_pos) #define CLKCTRL_EVSYS_CH4_bg (0x08 << CLKCTRL_ID_pos) #define CLKCTRL_EVSYS_CH5_bg (0x09 << CLKCTRL_ID_pos) #define CLKCTRL_EVSYS_CH6_bg (0x0A << CLKCTRL_ID_pos) #define CLKCTRL_EVSYS_CH7_bg (0x0B << CLKCTRL_ID_pos) #define CLKCTRL_SERCOMx_SLOW_bg (0x0C << CLKCTRL_ID_pos) #define CLKCTRL_SERCOM0_CORE_bg (0x0D << CLKCTRL_ID_pos) #define CLKCTRL_SERCOM1_CORE_bg (0x0E << CLKCTRL_ID_pos) #define CLKCTRL_SERCOM2_CORE_bg (0x0F << CLKCTRL_ID_pos) #define CLKCTRL_SERCOM3_CORE_bg (0x10 << CLKCTRL_ID_pos) #define CLKCTRL_SERCOM4_CORE_bg (0x11 << CLKCTRL_ID_pos) #define CLKCTRL_SERCOM5_CORE_bg (0x12 << CLKCTRL_ID_pos) #define CLKCTRL_TC0_TC1_bg (0x13 << CLKCTRL_ID_pos) #define CLKCTRL_TC2_TC3_bg (0x14 << CLKCTRL_ID_pos) #define CLKCTRL_TC4_TC5_bg (0x15 << CLKCTRL_ID_pos) #define CLKCTRL_TC6_TC7_bg (0x16 << CLKCTRL_ID_pos) #define CLKCTRL_ADC_bg (0x17 << CLKCTRL_ID_pos) #define CLKCTRL_AC_DIG_bg (0x18 << CLKCTRL_ID_pos) #define CLKCTRL_AC_ANA_bg (0x19 << CLKCTRL_ID_pos) #define CLKCTRL_DAC_bg (0x1A << CLKCTRL_ID_pos) #define CLKCTRL_PTC_bg (0x1B << CLKCTRL_ID_pos) //Register GENCTRL (in GCLK register) //GENCTRL[31:22] #define GENCTRL_RUNSTDBY_bp 21 #define GENCTRL_RUNSTDBY_bm (1 << GENCTRL_RUNSTDBY_bp) #define GENCTRL_DIVSEL_bp 20 #define GENCTRL_DIVSEL_bm (1 << GENCTRL_DIVSEL_bp) #define GENCTRL_OE_bp 19 #define GENCTRL_OE_bm (1 << GENCTRL_OE_bp) #define GENCTRL_OOV_bp 18 #define GENCTRL_OOV_bm (1 << GENCTRL_OOV_bp) #define GENCTRL_IDC_bp 17 #define GENCTRL_IDC_bm (1 << GENCTRL_IDC_bp) #define GENCTRL_GENEN_bp 16 #define GENCTRL_GENEN_bm (1 << GENCTRL_GENEN_bp) //GENCTRL[15:13] - reserved #define GENCTRL_SRC_pos 8 #define GENCTRL_SRC_msk (0x1F << GENCTRL_SRC_pos) #define GENCTRL_SRC_XOSC_bg (0x00 << GENCTRL_SRC_pos) #define GENCTRL_SRC_GCLKIN_bg (0x01 << GENCTRL_SRC_pos) #define GENCTRL_SRC_GCLKGEN1_bg (0x02 << GENCTRL_SRC_pos) #define GENCTRL_SRC_OSCULP32K_bg (0x03 << GENCTRL_SRC_pos) #define GENCTRL_SRC_OSC32K_bg (0x04 << GENCTRL_SRC_pos) #define GENCTRL_SRC_XOSC32K_bg (0x05 << GENCTRL_SRC_pos) #define GENCTRL_SRC_OSC8M_bg (0x06 << GENCTRL_SRC_pos) #define GENCTRL_SRC_DFLL48M_bg (0x07 << GENCTRL_SRC_pos) //GENCTRL[7:4] - reserved #define GENCTRL_ID_pos 0 #define GENCTRL_ID_msk (0x0F << GENCTRL_ID_pos) #define GENCTRL_GEN0_bg (0x00 << GENCTRL_ID_pos) #define GENCTRL_GEN1_bg (0x01 << GENCTRL_ID_pos) #define GENCTRL_GEN2_bg (0x02 << GENCTRL_ID_pos) #define GENCTRL_GEN3_bg (0x03 << GENCTRL_ID_pos) #define GENCTRL_GEN4_bg (0x04 << GENCTRL_ID_pos) #define GENCTRL_GEN5_bg (0x05 << GENCTRL_ID_pos) #define GENCTRL_GEN6_bg (0x06 << GENCTRL_ID_pos) #define GENCTRL_GEN7_bg (0x07 << GENCTRL_ID_pos) //CPUSEL (in PM register) - CPU Clock Select #define CPUSEL_CPUDIV_pos 0 #define CPUDIV1_bg (0x00 << CPUSEL_CPUDIV_pos) #define CPUDIV2_bg (0x01 << CPUSEL_CPUDIV_pos) #define CPUDIV4_bg (0x02 << CPUSEL_CPUDIV_pos) #define CPUDIV8_bg (0x03 << CPUSEL_CPUDIV_pos) #define CPUDIV16_bg (0x04 << CPUSEL_CPUDIV_pos) #define CPUDIV32_bg (0x05 << CPUSEL_CPUDIV_pos) #define CPUDIV64_bg (0x06 << CPUSEL_CPUDIV_pos) #define CPUDIV128_bg (0x07 << CPUSEL_CPUDIV_pos) //DFLLCTRL - DFLL48M Control 16 bit #define DFLLCTRL_QLDIS_bp 9 #define DFLLCTRL_QLDIS_bm (1 << DFLLCTRL_QLDIS_bp) #define DFLLCTRL_CCDIS_bp 8 #define DFLLCTRL_CCDIS_bm (1 << DFLLCTRL_CCDIS_bp) #define DFLLCTRL_ONDEMAND_bp 7 #define DFLLCTRL_ONDEMAND_bm (1 << DFLLCTRL_ONDEMAND_bp) #define DFLLCTRL_RUNSTDBY_bp 6 #define DFLLCTRL_RUNSTDBY_bm (1 << DFLLCTRL_RUNSTDBY_bp) //DFLLCTRL[5] - reserved #define DFLLCTRL_LLAW_bp 4 #define DFLLCTRL_LLAW_bm (1 << DFLLCTRL_LLAW_bp) #define DFLLCTRL_STABLE_bp 3 #define DFLLCTRL_STABLE_bm (1 << DFLLCTRL_STABLE_bp) #define DFLLCTRL_MODE_bp 2 #define DFLLCTRL_MODE_bm (1 << DFLLCTRL_MODE_bp) #define DFLLCTRL_ENABLE_bp 1 #define DFLLCTRL_ENABLE_bm (1 << DFLLCTRL_ENABLE_bp) //DFLLCTRL[0] - reserved /* //DFLLVAL - DFLL48M Value 32 bit #define DFLLVAL_DIFF_pos 16 #define DFLLVAL_DIFF_msk (0xFFFF << DFLLVAL_DIFF_pos) #define DFLLVAL_COARSE_pos 10 #define DFLLVAL_COARSE_msk (0x3F << DFLLVAL_COARSE_pos) #define DFLLVAL_FINE_pos 0 #define DFLLVAL_FINE_msk (0x3FF << DFLLVAL_FINE_pos) //DFLLMUL - DFLL48M Multiplier 32 bit #define DFLLMUL_CSTEP_pos 26 #define DFLLMUL_CSTEP_msk (0x3F << DFLLMUL_CSTEP_pos) #define DFLLMUL_FSTEP_pos 16 #define DFLLMUL_FSTEP_msk (0x3FF << DFLLMUL_FSTEP_pos) #define DFLLMUL_MULL_pos 0 #define DFLLMUL_MULL_msk (0xFFFF << DFLLMUL_MULL_pos) //DFLLSYNC - DFLL48M Synchronization 8 bit #define DFLLSYNC_READREQ_bp 7 #define DFLLSYNC_READREQ_bm (1 << DFLLSYNC_READREQ_bp) //DFLLSYNC[6:0] */ //DFLLVAL - DFLL48M Value 32 bit Errata!!! #define DFLLVAL_DIFF_pos 16 #define DFLLVAL_DIFF_msk (0xFFFF << DFLLVAL_DIFF_pos) #define DFLLVAL_COARSE_pos 8 #define DFLLVAL_COARSE_msk (0x1F << DFLLVAL_COARSE_pos) #define DFLLVAL_FINE_pos 0 #define DFLLVAL_FINE_msk (0xFF << DFLLVAL_FINE_pos) //DFLLMUL - DFLL48M Multiplier 32 bit #define DFLLMUL_CSTEP_pos 24 #define DFLLMUL_CSTEP_msk (0x1F << DFLLMUL_CSTEP_pos) #define DFLLMUL_FSTEP_pos 16 #define DFLLMUL_FSTEP_msk (0xFF << DFLLMUL_FSTEP_pos) #define DFLLMUL_MULL_pos 0 #define DFLLMUL_MULL_msk (0xFFFF << DFLLMUL_MULL_pos) //DFLLSYNC - DFLL48M Synchronization 8 bit #define DFLLSYNC_READREQ_bp 7 #define DFLLSYNC_READREQ_bm (1 << DFLLSYNC_READREQ_bp) //DFLLSYNC[6:0] //PCLKSR - Power and Clocks Status - 32 bit //PCLKSR[31:15] #define PCLKSR_B12SRDY_bp 14 #define PCLKSR_B12SRDY_bm (1 << PCLKSR_B12SRDY_bp) #define PCLKSR_BOD12DET_bp 13 #define PCLKSR_BOD12DET_bm (1 << PCLKSR_BOD12DET_bp) #define PCLKSR_BOD12RDY_bp 12 #define PCLKSR_BOD12RDY_bm (1 << PCLKSR_BOD12RDY_bp) #define PCLKSR_B33SRDY_bp 11 #define PCLKSR_B33SRDY_bm (1 << PCLKSR_B33SRDY_bp) #define PCLKSR_BOD33DET_bp 10 #define PCLKSR_BOD33DET_bm (1 << PCLKSR_BOD33DET_bp) #define PCLKSR_BOD33RDY_bp 9 #define PCLKSR_BOD33RDY_bm (1 << PCLKSR_BOD33RDY_bp) #define PCLKSR_DFLLRCS_bp 8 #define PCLKSR_DFLLRCS_bm (1 << PCLKSR_DFLLRCS_bp) #define PCLKSR_DFLLLCKC_bp 7 #define PCLKSR_DFLLLCKC_bm (1 << PCLKSR_DFLLLCKC_bp) #define PCLKSR_DFLLLCKF_bp 6 #define PCLKSR_DFLLLCKF_bm (1 << PCLKSR_DFLLLCKF_bp) #define PCLKSR_DFLLOOB_bp 5 #define PCLKSR_DFLLOOB_bm (1 << PCLKSR_DFLLOOB_bp) #define PCLKSR_DFLLRDY_bp 4 #define PCLKSR_DFLLRDY_bm (1 << PCLKSR_DFLLRDY_bp) #define PCLKSR_OSC8MRDY_bp 3 #define PCLKSR_OSC8MRDY_bm (1 << PCLKSR_OSC8MRDY_bp) #define PCLKSR_OSC32KRDY_bp 2 #define PCLKSR_OSC32KRDY_bm (1 << PCLKSR_OSC32KRDY_bp) #define PCLKSR_XOSC32KRDY_bp 1 #define PCLKSR_XOSC32KRDY_bm (1 << PCLKSR_XOSC32KRDY_bp) #define PCLKSR_XOSCRDY_bp 0 #define PCLKSR_XOSCRDY_bm (1 << PCLKSR_XOSCRDY_bp) //XOSC32K - 32kHz External Crystal Oscillator (XOSC32K) Control 16 bit //XOSC32K[15:13] - reserved #define XOSC32K_WRTLOCK_bp 12 #define XOSC32K_WRTLOCK_bm (1 << XOSC32K_WRTLOCK_bp) //XOSC32K[11] - reserved #define XOSC32K_STARTUP_pos 8 #define XOSC32K_STARTUP_msk (0x7 << XOSC32K_STARTUP_pos) #define XOSC32K_STARTUP_122us_bg (0x00 << XOSC32K_STARTUP_pos) #define XOSC32K_STARTUP_1068us_bg (0x01 << XOSC32K_STARTUP_pos) #define XOSC32K_STARTUP_62592us_bg (0x02 << XOSC32K_STARTUP_pos) #define XOSC32K_STARTUP_125092us_bg (0x03 << XOSC32K_STARTUP_pos) #define XOSC32K_STARTUP_500092us_bg (0x04 << XOSC32K_STARTUP_pos) #define XOSC32K_STARTUP_1000092us_bg (0x05 << XOSC32K_STARTUP_pos) #define XOSC32K_STARTUP_2000092us_bg (0x06 << XOSC32K_STARTUP_pos) #define XOSC32K_STARTUP_4000092us_bg (0x07 << XOSC32K_STARTUP_pos) #define XOSC32K_ONDEMAND_bp 7 #define XOSC32K_ONDEMAND_bm (1 << XOSC32K_ONDEMAND_bp) #define XOSC32K_RUNSTDBY_bp 6 #define XOSC32K_RUNSTDBY_bm (1 << XOSC32K_RUNSTDBY_bp) #define XOSC32K_AAMPEN_bp 5 #define XOSC32K_AAMPEN_bm (1 << XOSC32K_AAMPEN_bp) #define XOSC32K_EN1K_bp 4 #define XOSC32K_EN1K_bm (1 << XOSC32K_EN1K_bp) #define XOSC32K_EN32K_bp 3 #define XOSC32K_EN32K_bm (1 << XOSC32K_EN32K_bp) #define XOSC32K_XTALEN_bp 2 #define XOSC32K_XTALEN_bm (1 << XOSC32K_XTALEN_bp) #define XOSC32K_ENABLE_bp 1 #define XOSC32K_ENABLE_bm (1 << XOSC32K_ENABLE_bp) //XOSC32K[0] - reserved //OSC32K - 32kHz Internal Oscillator Control //OSC32K[31:23] - reserved #define OSC32K_CALIB_pos 16 #define OSC32K_CALIB_msk 0x3F //OSC32K[15:13] - reserved #define OSC32K_WRTLOCK_bp 12 #define OSC32K_WRTLOCK_bm (1 << OSC32K_WRTLOCK_bp) //OSC32K[11] - reserved #define OSC32K_STARTUP_pos 8 #define OSC32K_STARTUP_msk 0x07 #define OSC32K_STARTUP_92us_bg (0x00 << OSC32K_STARTUP_pos) #define OSC32K_STARTUP_122us_bg (0x01 << OSC32K_STARTUP_pos) #define OSC32K_STARTUP_183us_bg (0x02 << OSC32K_STARTUP_pos) #define OSC32K_STARTUP_305us_bg (0x03 << OSC32K_STARTUP_pos) #define OSC32K_STARTUP_549us_bg (0x04 << OSC32K_STARTUP_pos) #define OSC32K_STARTUP_1038us_bg (0x05 << OSC32K_STARTUP_pos) #define OSC32K_STARTUP_2014us_bg (0x06 << OSC32K_STARTUP_pos) #define OSC32K_STARTUP_3967us_bg (0x07 << OSC32K_STARTUP_pos) #define OSC32K_ONDEMAND_bp 7 #define OSC32K_ONDEMAND_bm (1 << OSC32K_ONDEMAND_bp) #define OSC32K_RUNSTDBY_bp 6 #define OSC32K_RUNSTDBY_bm (1 << OSC32K_RUNSTDBY_bp) //OSC32K[5:4] - reserved #define OSC32K_EN1K_bp 3 #define OSC32K_EN1K_bm (1 << OSC32K_EN1K_bp) #define OSC32K_EN32K_bp 2 #define OSC32K_EN32K_bm (1 << OSC32K_EN32K_bp) #define OSC32K_ENABLE_bp 1 #define OSC32K_ENABLE_bm (1 << OSC32K_ENABLE_bp) //OSC32K[0] - reserved