; generated by Component: ARM Compiler 5.04 update 1 (build 49) Tool: ArmCC [5040049]
; commandline ArmCC [--list --debug -c --asm --interleave -o.\output\system_stm32f4xx.o --asm_dir=.\List\ --list_dir=.\List\ --depend=.\output\system_stm32f4xx.d --cpu=Cortex-M4.fp --apcs=interwork -O0 -I.\inc -I.\STM -I"C:\Program Files (x86)\Micro\Keil\ARM\RV31\INC" -I"C:\Program Files (x86)\Micro\Keil\ARM\PACK\ARM\CMSIS\3.20.4\CMSIS\Include" -I"C:\Program Files (x86)\Micro\Keil\ARM\PACK\Keil\STM32F4xx_DFP\1.0.6\Device\Include" -DSTM32F40_41xxx -DSTM32F40XX --omf_browse=.\output\system_stm32f4xx.crf STM\system_stm32f4xx.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  SetSysClock PROC
;;;346      */
;;;347    static void SetSysClock(void)
000000  b50c              PUSH     {r2,r3,lr}
;;;348    {
;;;349    /******************************************************************************/
;;;350    /*            PLL (clocked by HSE) used as System clock source                */
;;;351    /******************************************************************************/
;;;352      __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
000002  2000              MOVS     r0,#0
000004  9001              STR      r0,[sp,#4]
000006  9000              STR      r0,[sp,#0]
;;;353      
;;;354      /* Enable HSE */
;;;355      RCC->CR |= ((uint32_t)RCC_CR_HSEON);
000008  4876              LDR      r0,|L1.484|
00000a  6800              LDR      r0,[r0,#0]
00000c  f4403080          ORR      r0,r0,#0x10000
000010  4974              LDR      r1,|L1.484|
000012  6008              STR      r0,[r1,#0]
;;;356     
;;;357      /* Wait till HSE is ready and if Time out is reached exit */
;;;358      do
000014  bf00              NOP      
                  |L1.22|
;;;359      {
;;;360        HSEStatus = RCC->CR & RCC_CR_HSERDY;
000016  4873              LDR      r0,|L1.484|
000018  6800              LDR      r0,[r0,#0]
00001a  f4003000          AND      r0,r0,#0x20000
00001e  9000              STR      r0,[sp,#0]
;;;361        StartUpCounter++;
000020  9801              LDR      r0,[sp,#4]
000022  1c40              ADDS     r0,r0,#1
000024  9001              STR      r0,[sp,#4]
;;;362      } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
000026  9800              LDR      r0,[sp,#0]
000028  b918              CBNZ     r0,|L1.50|
00002a  9801              LDR      r0,[sp,#4]
00002c  f5b06fc0          CMP      r0,#0x600
000030  d1f1              BNE      |L1.22|
                  |L1.50|
;;;363    
;;;364      if ((RCC->CR & RCC_CR_HSERDY) != RESET)
000032  486c              LDR      r0,|L1.484|
000034  6800              LDR      r0,[r0,#0]
000036  f4003000          AND      r0,r0,#0x20000
00003a  b110              CBZ      r0,|L1.66|
;;;365      {
;;;366        HSEStatus = (uint32_t)0x01;
00003c  2001              MOVS     r0,#1
00003e  9000              STR      r0,[sp,#0]
000040  e001              B        |L1.70|
                  |L1.66|
;;;367      }
;;;368      else
;;;369      {
;;;370        HSEStatus = (uint32_t)0x00;
000042  2000              MOVS     r0,#0
000044  9000              STR      r0,[sp,#0]
                  |L1.70|
;;;371      }
;;;372    
;;;373      if (HSEStatus == (uint32_t)0x01)
000046  9800              LDR      r0,[sp,#0]
000048  2801              CMP      r0,#1
00004a  d146              BNE      |L1.218|
;;;374      {
;;;375        /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
;;;376        RCC->APB1ENR |= RCC_APB1ENR_PWREN;
00004c  4865              LDR      r0,|L1.484|
00004e  3040              ADDS     r0,r0,#0x40
000050  6800              LDR      r0,[r0,#0]
000052  f0405080          ORR      r0,r0,#0x10000000
000056  4963              LDR      r1,|L1.484|
000058  3140              ADDS     r1,r1,#0x40
00005a  6008              STR      r0,[r1,#0]
;;;377        PWR->CR |= PWR_CR_VOS;
00005c  4862              LDR      r0,|L1.488|
00005e  6800              LDR      r0,[r0,#0]
000060  f4404040          ORR      r0,r0,#0xc000
000064  4960              LDR      r1,|L1.488|
000066  6008              STR      r0,[r1,#0]
;;;378    
;;;379        /* HCLK = SYSCLK / 1*/
;;;380        RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
000068  485e              LDR      r0,|L1.484|
00006a  3008              ADDS     r0,r0,#8
00006c  6800              LDR      r0,[r0,#0]
00006e  495d              LDR      r1,|L1.484|
000070  3108              ADDS     r1,r1,#8
000072  6008              STR      r0,[r1,#0]
;;;381          
;;;382        /* PCLK2 = HCLK / 2*/
;;;383        RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
000074  4608              MOV      r0,r1
000076  6800              LDR      r0,[r0,#0]
000078  f4404000          ORR      r0,r0,#0x8000
00007c  6008              STR      r0,[r1,#0]
;;;384        
;;;385        /* PCLK1 = HCLK / 4*/
;;;386        RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
00007e  4608              MOV      r0,r1
000080  6800              LDR      r0,[r0,#0]
000082  f44050a0          ORR      r0,r0,#0x1400
000086  6008              STR      r0,[r1,#0]
;;;387    
;;;388        /* Configure the main PLL */
;;;389        RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
000088  4858              LDR      r0,|L1.492|
00008a  1f09              SUBS     r1,r1,#4
00008c  6008              STR      r0,[r1,#0]
;;;390                       (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
;;;391    
;;;392        /* Enable the main PLL */
;;;393        RCC->CR |= RCC_CR_PLLON;
00008e  1f08              SUBS     r0,r1,#4
000090  6800              LDR      r0,[r0,#0]
000092  f0407080          ORR      r0,r0,#0x1000000
000096  1f09              SUBS     r1,r1,#4
000098  6008              STR      r0,[r1,#0]
;;;394    
;;;395        /* Wait till the main PLL is ready */
;;;396        while((RCC->CR & RCC_CR_PLLRDY) == 0)
00009a  bf00              NOP      
                  |L1.156|
00009c  4851              LDR      r0,|L1.484|
00009e  6800              LDR      r0,[r0,#0]
0000a0  f0007000          AND      r0,r0,#0x2000000
0000a4  2800              CMP      r0,#0
0000a6  d0f9              BEQ      |L1.156|
;;;397        {
;;;398        }
;;;399       
;;;400        /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
;;;401        FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
0000a8  f2406005          MOV      r0,#0x605
0000ac  4950              LDR      r1,|L1.496|
0000ae  6008              STR      r0,[r1,#0]
;;;402    
;;;403        /* Select the main PLL as system clock source */
;;;404        RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
0000b0  484c              LDR      r0,|L1.484|
0000b2  3008              ADDS     r0,r0,#8
0000b4  6800              LDR      r0,[r0,#0]
0000b6  f0200003          BIC      r0,r0,#3
0000ba  494a              LDR      r1,|L1.484|
0000bc  3108              ADDS     r1,r1,#8
0000be  6008              STR      r0,[r1,#0]
;;;405        RCC->CFGR |= RCC_CFGR_SW_PLL;
0000c0  4608              MOV      r0,r1
0000c2  6800              LDR      r0,[r0,#0]
0000c4  f0400002          ORR      r0,r0,#2
0000c8  6008              STR      r0,[r1,#0]
;;;406    
;;;407        /* Wait till the main PLL is used as system clock source */
;;;408        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
0000ca  bf00              NOP      
                  |L1.204|
0000cc  4845              LDR      r0,|L1.484|
0000ce  3008              ADDS     r0,r0,#8
0000d0  6800              LDR      r0,[r0,#0]
0000d2  f000000c          AND      r0,r0,#0xc
0000d6  2808              CMP      r0,#8
0000d8  d1f8              BNE      |L1.204|
                  |L1.218|
;;;409        {
;;;410        }
;;;411      }
;;;412      else
;;;413      { /* If HSE fails to start-up, the application will have wrong clock
;;;414             configuration. User can add here some code to deal with this error */
;;;415      }
;;;416    
;;;417    }
0000da  bd0c              POP      {r2,r3,pc}
;;;418    
                          ENDP

                  SystemInit PROC
;;;213      */
;;;214    void SystemInit(void)
0000dc  b510              PUSH     {r4,lr}
;;;215    {
;;;216      /* FPU settings ------------------------------------------------------------*/
;;;217      #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
;;;218        SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
0000de  4845              LDR      r0,|L1.500|
0000e0  6800              LDR      r0,[r0,#0]
0000e2  f4400070          ORR      r0,r0,#0xf00000
0000e6  4943              LDR      r1,|L1.500|
0000e8  6008              STR      r0,[r1,#0]
;;;219      #endif
;;;220      /* Reset the RCC clock configuration to the default reset state ------------*/
;;;221      /* Set HSION bit */
;;;222      RCC->CR |= (uint32_t)0x00000001;
0000ea  483e              LDR      r0,|L1.484|
0000ec  6800              LDR      r0,[r0,#0]
0000ee  f0400001          ORR      r0,r0,#1
0000f2  493c              LDR      r1,|L1.484|
0000f4  6008              STR      r0,[r1,#0]
;;;223    
;;;224      /* Reset CFGR register */
;;;225      RCC->CFGR = 0x00000000;
0000f6  2000              MOVS     r0,#0
0000f8  493a              LDR      r1,|L1.484|
0000fa  3108              ADDS     r1,r1,#8
0000fc  6008              STR      r0,[r1,#0]
;;;226    
;;;227      /* Reset HSEON, CSSON and PLLON bits */
;;;228      RCC->CR &= (uint32_t)0xFEF6FFFF;
0000fe  4839              LDR      r0,|L1.484|
000100  6800              LDR      r0,[r0,#0]
000102  493d              LDR      r1,|L1.504|
000104  4008              ANDS     r0,r0,r1
000106  4937              LDR      r1,|L1.484|
000108  6008              STR      r0,[r1,#0]
;;;229    
;;;230      /* Reset PLLCFGR register */
;;;231      RCC->PLLCFGR = 0x24003010;
00010a  483c              LDR      r0,|L1.508|
00010c  1d09              ADDS     r1,r1,#4
00010e  6008              STR      r0,[r1,#0]
;;;232    
;;;233      /* Reset HSEBYP bit */
;;;234      RCC->CR &= (uint32_t)0xFFFBFFFF;
000110  1f08              SUBS     r0,r1,#4
000112  6800              LDR      r0,[r0,#0]
000114  f4202080          BIC      r0,r0,#0x40000
000118  1f09              SUBS     r1,r1,#4
00011a  6008              STR      r0,[r1,#0]
;;;235    
;;;236      /* Disable all interrupts */
;;;237      RCC->CIR = 0x00000000;
00011c  2000              MOVS     r0,#0
00011e  4931              LDR      r1,|L1.484|
000120  310c              ADDS     r1,r1,#0xc
000122  6008              STR      r0,[r1,#0]
;;;238    
;;;239    #ifdef DATA_IN_ExtSRAM
;;;240      SystemInit_ExtMemCtl(); 
;;;241    #endif /* DATA_IN_ExtSRAM */
;;;242             
;;;243      /* Configure the System clock source, PLL Multiplier and Divider factors, 
;;;244         AHB/APBx prescalers and Flash settings ----------------------------------*/
;;;245      SetSysClock();
000124  f7fffffe          BL       SetSysClock
;;;246    
;;;247      /* Configure the Vector Table location add offset address ------------------*/
;;;248    #ifdef VECT_TAB_SRAM
;;;249      SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
;;;250    #else
;;;251      SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
000128  f04f6000          MOV      r0,#0x8000000
00012c  4931              LDR      r1,|L1.500|
00012e  3980              SUBS     r1,r1,#0x80
000130  6008              STR      r0,[r1,#0]
;;;252    #endif
;;;253    }
000132  bd10              POP      {r4,pc}
;;;254    
                          ENDP

                  SystemCoreClockUpdate PROC
;;;290      */
;;;291    void SystemCoreClockUpdate(void)
000134  b570              PUSH     {r4-r6,lr}
;;;292    {
;;;293      uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
000136  2000              MOVS     r0,#0
000138  2200              MOVS     r2,#0
00013a  2302              MOVS     r3,#2
00013c  2400              MOVS     r4,#0
00013e  2102              MOVS     r1,#2
;;;294      
;;;295      /* Get SYSCLK source -------------------------------------------------------*/
;;;296      tmp = RCC->CFGR & RCC_CFGR_SWS;
000140  4d28              LDR      r5,|L1.484|
000142  3508              ADDS     r5,r5,#8
000144  682d              LDR      r5,[r5,#0]
000146  f005000c          AND      r0,r5,#0xc
;;;297    
;;;298      switch (tmp)
00014a  b120              CBZ      r0,|L1.342|
00014c  2804              CMP      r0,#4
00014e  d006              BEQ      |L1.350|
000150  2808              CMP      r0,#8
000152  d134              BNE      |L1.446|
000154  e007              B        |L1.358|
                  |L1.342|
;;;299      {
;;;300        case 0x00:  /* HSI used as system clock source */
;;;301          SystemCoreClock = HSI_VALUE;
000156  4d2a              LDR      r5,|L1.512|
000158  4e2a              LDR      r6,|L1.516|
00015a  6035              STR      r5,[r6,#0]  ; SystemCoreClock
;;;302          break;
00015c  e033              B        |L1.454|
                  |L1.350|
;;;303        case 0x04:  /* HSE used as system clock source */
;;;304          SystemCoreClock = HSE_VALUE;
00015e  4d2a              LDR      r5,|L1.520|
000160  4e28              LDR      r6,|L1.516|
000162  6035              STR      r5,[r6,#0]  ; SystemCoreClock
;;;305          break;
000164  e02f              B        |L1.454|
                  |L1.358|
;;;306        case 0x08:  /* PLL used as system clock source */
;;;307    
;;;308          /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
;;;309             SYSCLK = PLL_VCO / PLL_P
;;;310             */    
;;;311          pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
000166  4d1f              LDR      r5,|L1.484|
000168  1d2d              ADDS     r5,r5,#4
00016a  682d              LDR      r5,[r5,#0]
00016c  f3c55480          UBFX     r4,r5,#22,#1
;;;312          pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
000170  4d1c              LDR      r5,|L1.484|
000172  1d2d              ADDS     r5,r5,#4
000174  682d              LDR      r5,[r5,#0]
000176  f005013f          AND      r1,r5,#0x3f
;;;313          
;;;314          if (pllsource != 0)
00017a  b154              CBZ      r4,|L1.402|
;;;315          {
;;;316            /* HSE used as PLL clock source */
;;;317            pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
00017c  4d22              LDR      r5,|L1.520|
00017e  fbb5f5f1          UDIV     r5,r5,r1
000182  4e18              LDR      r6,|L1.484|
000184  1d36              ADDS     r6,r6,#4
000186  6836              LDR      r6,[r6,#0]
000188  f3c61688          UBFX     r6,r6,#6,#9
00018c  fb05f206          MUL      r2,r5,r6
000190  e009              B        |L1.422|
                  |L1.402|
;;;318          }
;;;319          else
;;;320          {
;;;321            /* HSI used as PLL clock source */
;;;322            pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
000192  4d1b              LDR      r5,|L1.512|
000194  fbb5f5f1          UDIV     r5,r5,r1
000198  4e12              LDR      r6,|L1.484|
00019a  1d36              ADDS     r6,r6,#4
00019c  6836              LDR      r6,[r6,#0]
00019e  f3c61688          UBFX     r6,r6,#6,#9
0001a2  fb05f206          MUL      r2,r5,r6
                  |L1.422|
;;;323          }
;;;324    
;;;325          pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
0001a6  4d0f              LDR      r5,|L1.484|
0001a8  1d2d              ADDS     r5,r5,#4
0001aa  682d              LDR      r5,[r5,#0]
0001ac  f3c54501          UBFX     r5,r5,#16,#2
0001b0  1c6d              ADDS     r5,r5,#1
0001b2  006b              LSLS     r3,r5,#1
;;;326          SystemCoreClock = pllvco/pllp;
0001b4  fbb2f5f3          UDIV     r5,r2,r3
0001b8  4e12              LDR      r6,|L1.516|
0001ba  6035              STR      r5,[r6,#0]  ; SystemCoreClock
;;;327          break;
0001bc  e003              B        |L1.454|
                  |L1.446|
;;;328        default:
;;;329          SystemCoreClock = HSI_VALUE;
0001be  4d10              LDR      r5,|L1.512|
0001c0  4e10              LDR      r6,|L1.516|
0001c2  6035              STR      r5,[r6,#0]  ; SystemCoreClock
;;;330          break;
0001c4  bf00              NOP      
                  |L1.454|
0001c6  bf00              NOP                            ;302
;;;331      }
;;;332      /* Compute HCLK frequency --------------------------------------------------*/
;;;333      /* Get HCLK prescaler */
;;;334      tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
0001c8  4d06              LDR      r5,|L1.484|
0001ca  3508              ADDS     r5,r5,#8
0001cc  682d              LDR      r5,[r5,#0]
0001ce  f3c51503          UBFX     r5,r5,#4,#4
0001d2  4e0e              LDR      r6,|L1.524|
0001d4  5d70              LDRB     r0,[r6,r5]
;;;335      /* HCLK frequency */
;;;336      SystemCoreClock >>= tmp;
0001d6  4d0b              LDR      r5,|L1.516|
0001d8  682d              LDR      r5,[r5,#0]  ; SystemCoreClock
0001da  40c5              LSRS     r5,r5,r0
0001dc  4e09              LDR      r6,|L1.516|
0001de  6035              STR      r5,[r6,#0]  ; SystemCoreClock
;;;337    }
0001e0  bd70              POP      {r4-r6,pc}
;;;338    
                          ENDP

0001e2  0000              DCW      0x0000
                  |L1.484|
                          DCD      0x40023800
                  |L1.488|
                          DCD      0x40007000
                  |L1.492|
                          DCD      0x07405408
                  |L1.496|
                          DCD      0x40023c00
                  |L1.500|
                          DCD      0xe000ed88
                  |L1.504|
                          DCD      0xfef6ffff
                  |L1.508|
                          DCD      0x24003010
                  |L1.512|
                          DCD      0x00f42400
                  |L1.516|
                          DCD      SystemCoreClock
                  |L1.520|
                          DCD      0x007a1200
                  |L1.524|
                          DCD      AHBPrescTable

                          AREA ||.data||, DATA, ALIGN=2

                  SystemCoreClock
                          DCD      0x0a037a00
                  AHBPrescTable
000004  00000000          DCB      0x00,0x00,0x00,0x00
000008  00000000          DCB      0x00,0x00,0x00,0x00
00000c  01020304          DCB      0x01,0x02,0x03,0x04
000010  06070809          DCB      0x06,0x07,0x08,0x09

;*** Start embedded assembler ***

#line 1 "STM\\system_stm32f4xx.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___18_system_stm32f4xx_c_5d646a67____REV16|
#line 129 "C:\\Program Files (x86)\\Micro\\Keil\\ARM\\PACK\\ARM\\CMSIS\\3.20.4\\CMSIS\\Include\\core_cmInstr.h"
|__asm___18_system_stm32f4xx_c_5d646a67____REV16| PROC
#line 130

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___18_system_stm32f4xx_c_5d646a67____REVSH|
#line 144
|__asm___18_system_stm32f4xx_c_5d646a67____REVSH| PROC
#line 145

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
