void tim1_init(void)
{ 
  NVIC_InitTypeDef NVIC_InitStructure; //create NVIC structure
  TIM_BDTRInitTypeDef bdtr;
  TIM_BDTRStructInit(&bdtr);
 

  RCC->APB2ENR |= RCC_APB2ENR_IOPBEN;       // Enable GPIOB clocking
  RCC->APB2ENR |= RCC_APB2ENR_IOPAEN;       // Enable GPIOA clocking
  RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;       // Enable TIM1 clocking
  RCC->APB2ENR |= RCC_APB2ENR_AFIOEN;       // Enable AFIO clocking

  //////////////////////////////////////////////////////////////////////////////// GPIO
  GPIOB->CRL  = (GPIO_CRL_MODE0 | 
                 GPIO_CRL_CNF0_1);    // PB0 - Output mode 50 MHz 
  GPIOB->CRL &= (~GPIO_CRL_CNF0_0);   // and alternate push-pull

  //----------------------------------------
  GPIOA->CRL |= (GPIO_CRL_MODE7 | GPIO_CRL_CNF7_1); // PA7 - Output mode 50 MHz 
  GPIOA->CRL &= (~GPIO_CRL_CNF7_0); // and alternate push-pull
  //----------------------------------------
  GPIOA->CRH |= (GPIO_CRH_MODE8 | 
                 GPIO_CRH_MODE9 | 
                 GPIO_CRH_CNF8_1 | 
                 GPIO_CRH_CNF9_1); // PA8, PA9 - Output mode 50 MHz
  GPIOA->CRH &= (~(GPIO_CRH_CNF8_0 | 
                   GPIO_CRH_CNF9_0)); // and alternate push-pull
  GPIOA->ODR = 0x0000;

//---------------------------------------
  AFIO->MAPR |= AFIO_MAPR_TIM1_REMAP_0;
  AFIO->MAPR &= (~AFIO_MAPR_TIM1_REMAP_1);

  //////////////////////////////////////////////////////////////////////////////// PWM Timer 1
  TIM1->CR1 = TIM_CounterMode_CenterAligned1|TIM_CR1_ARPE|TIM_CR1_URS;
  TIM1->RCR = 1;
  TIM1->PSC = 0;
  TIM1->ARR = 0x00FF;
  TIM1->CR2 = TIM_CR2_CCPC;
  
  TIM1->CCR1 = 0;
  TIM1->CCR2 = 0;
  TIM1->CCR3 = 0;
  TIM1->CCR4 = 0;


  TIM1->CCER = TIM_CCER_CC1E|TIM_CCER_CC1NE;
  TIM1->CCER|= TIM_CCER_CC2E|TIM_CCER_CC2NE;

  TIM1->CCMR1 = TIM_OCMode_PWM1;
  TIM1->CCMR2 = TIM_OCMode_PWM1;
  TIM1->EGR  = TIM_EGR_COMG;     

 

 
  bdtr.TIM_AutomaticOutput = TIM_AutomaticOutput_Enable;
  bdtr.TIM_DeadTime = 4;
  bdtr.TIM_LOCKLevel = TIM_LOCKLevel_2;
  bdtr.TIM_OSSRState = TIM_OSSRState_Enable;
  bdtr.TIM_OSSIState = TIM_OSSIState_Enable;
  


  TIM_BDTRConfig(TIM1, &bdtr);
  

  

 
  NVIC_InitStructure.NVIC_IRQChannel = TIM1_UP_IRQn;
  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
  NVIC_Init(&NVIC_InitStructure);
  		
  TIM_ITConfig(TIM1, TIM_IT_Update | TIM_IT_Trigger | TIM_IT_Break , ENABLE);	 
  TIM1->CR1 |= TIM_CR1_CEN;
  }


  void TIM1_UP_IRQHandler(void)
  {	 
  
#define s_step 312
static u8 i=0;
static u8 rck=0, dir;
static u8 ccr2 , ccr1;

static const u8 s_table [s_step/2]=
{0,2,5,7,10,12,15,18,20,23,25,28,30,33,36,38,41,43,46,48,51,
53,56,58,61,63,66,68,71,73,76,78,81,83,86,88,91,93,95,98,100,103,
105,107,110,112,114,117,119,121,123,126,128,130,132,135,137,139,141,143,145,147,150,
152,154,156,158,160,162,164,166,168,170,172,174,175,177,179,181,183,185,186,188,190,
192,193,195,197,198,200,201,203,205,206,208,209,211,212,214,215,216,218,219,220,222,
223,224,225,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,243,
244,245,246,246,247,248,248,249,249,250,251,251,252,252,252,253,253,253,254,254,254,
255,255,255,255,255,255,255,255,255};

 if(!i)
 {
 dir=1;i=1;
   if(rck)
   {
    rck=0;
    TIM1->CCMR1 = TIM_OCMode_PWM1;
    TIM1->CCMR2 = 0x40; 
   }
   else
   {
    rck=1;
    TIM1->CCMR1 = 0x40; 
    TIM1->CCMR2 = TIM_OCMode_PWM1;
   }

    TIM1->EGR|=TIM_EGR_COMG; 
 }
 else if((dir)&&(i<s_step/2-1))
  {
    i++;
    TIM1->CCR1=TIM1->CCR2=s_table[i];
  }
 else
  {
    dir=0; i--;
    TIM1->CCR1=TIM1->CCR2=s_table[i];
  }

    TIM1->SR = 0;  

  }