.device ATmega8
.include "m8def.inc"
.def	mc8u	=r16	
.def	mp8u	=r17
.def	m8uL	=r17
.def	m8uH	=r18
.def	mcnt8u	=r19
.def	drem16uL=r20
.def	drem16uH=r21
.def	dres16uL=r22
.def	dres16uH=r23
.def	dd16uL	=r22
.def	dd16uH	=r23
.def	dv16uL	=r24
.def	dv16uH	=r25
.def	dcnt16u	=r26
.def    temp=r27
.def    n=r28
.def    s_T0=r29
.def    l=r16
.equ seg	=PORTB
.CSEG
.org $0000
	rjmp Start
.org $0001
    in s_T0, TCNT0
    ldi	temp,(0<<CS02)|(0<<CS01)|(0<<CS00)
    out	TCCR0,temp
    rjmp Obr
    reti;
.org $0006
    rjmp Obr_T1
	reti;
.org $0009
	inc n
	reti;

Start:
ldi temp, High(RAMEND)
out SPH,temp
ldi temp, Low(RAMEND)
out SPL,temp
ldi n,0
ldi l,0
ldi temp, (1<<PB0)|(1<<PB1)|(1<<PB2)|(1<<PB3)|(1<<PB4)|(1<<PB5)
out DDRB,temp
ldi temp,(1<<ISC00)|(1<<ISC01)
out MCUCR,temp
ldi temp,(1<<INT0)
out GICR,temp
ldi	temp,(1<<OCIE1A)|(1<<TOIE0)
out	TIMSK,temp
ldi	temp,(1<<CS02)|(0<<CS01)|(1<<CS00)
out	TCCR0,temp
sei

loop:
rjmp loop

Obr:
ldi	temp,(0<<CS12)|(0<<CS11)|(0<<CS10)
out	TCCR1B,temp
ldi mc8u,255
mov mp8u,n
rcall MUL8x8
add m8uL, s_T0
brcs per
m:
mov dd16uL,m8uL
mov dd16uH,m8uH
ldi dv16uL, 64
ldi dv16uH, 0
rcall DIV16
mov r16,dres16uH
mov r17,dres16uL
out	OCR1AH,r16
out	OCR1AL,r17
ldi n,0
ldi l,0
clr r24
ldi	ZH,High(seg_table*2)
ldi	ZL,Low(seg_table*2)
add	ZL,l 
adc ZH,r24
lpm						
out	seg,r0				
inc l
ldi	temp,(1<<PSR10)
out	SFIOR,temp
OUT TCNT0,temp
ldi	temp,(1<<CS02)|(0<<CS01)|(1<<CS00)
out	TCCR0,temp	
ldi	temp,(1<<OCIE1A)|(1<<TOIE0)
out	TIMSK,temp
clr r24
clr r17
OUT	TCNT1H,R24
OUT	TCNT1L,R17
ldi	temp,(1<<CS12)|(0<<CS11)|(1<<CS10)|(1<<WGM12)
out	TCCR1B,temp
reti	

per:
ldi temp, 1
add m8uH,temp
rjmp m

Obr_T1:
sei
clr r24
ldi	ZH,High(seg_table*2)
ldi	ZL,Low(seg_table*2)
add	ZL,l 
adc ZH,r24
lpm					
out	seg,r0			
inc l
reti


MUL8x8:
mpy8u:	clr	m8uH	
	ldi	mcnt8u,8	
	lsr	mp8u		
m8u_1:	brcc	m8u_2	
	add 	m8uH,mc8u	
m8u_2:	ror	m8uH	
	ror	m8uL		
	dec	mcnt8u	
	brne	m8u_1	
	ret

DIV16:
div16u:	clr	drem16uL	
	sub	drem16uH,drem16uH
	ldi	dcnt16u,17	
d16u_1:	rol	dd16uL	
	rol	dd16uH
	dec	dcnt16u	
	brne	d16u_2	
	ret			
d16u_2:	rol	drem16uL	
	rol	drem16uH
	sub	drem16uL,dv16uL	
	sbc	drem16uH,dv16uH	
	brcc	d16u_3		
	add	drem16uL,dv16uL
	adc	drem16uH,dv16uH
	clc		
	rjmp	d16u_1	
d16u_3:	sec		
	rjmp	d16u_1
	seg_table:
.db $0,$0,$0,$0,$0,$0,$c,$c,$0,$0,$0,$0,$0,$0,$0,$0,$0,$0,$c,$c,$c,$c,$c,$c,$c,$c,$c,$c,$c,$c,$c,$c,$c,$c,$c,$c,$c,$c,$c,$c,$c,$c,$c,$c,$0,$0,$0,$0,$0,$0,$0,$0,$0,$0,$c,$c,$0,$0,$0,$0,$0,$0
.exit