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This is freeware. There are no guarantees as to the quality or
reliability of this program. Use it entirely at your own risk.
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SPILEP25.EXE - "SPI Large EEPROM Programmer" - A PC Parallel Port Serial
EEPROM Programmer for DOS by Phil at http://www.retroleum.co.uk '07

Used for:

Reading/writing/erasing large SPI EEPROMs with 256 byte write pages such
as the Winbond W25XXX series, or ST M25PXXX series chips.
(Other SPI EEPROMs such as the AT26FXXX series are not currently
compatible as their protocol is subtly different.)
 
Files:

SPILEP25.EXE - the program (There are no command line options).
SPICFG.TXT - configuration file

Configuration:

By editing "spicfg.txt", user can set PC parallel port address, port bits
used for SPI lines, polarity of lines and transfer speed to match target
interface. (See "interface.png" for an example interface.)

ID bytes for EEPROM type can be updated for new EEPROMs of the same series.
Config is currently set up for the following devices:

Chip: ID: 
----- --  
25X10 10h 
25x20 11h 
25X40 12h 
25X80 13h 
25x16 14h
25x32 15h
25x64 16h

See your device datasheet for other chip IDs (IE: response to command $AB)


Notes on config file: "spicfg.txt"
-----------------------------------

* Do not change the order of the entries or remove marker chars (%,# etc)
* File must be < 1024 bytes
* All numbers are in hex
* Words must be zero padded to 4 digits, bytes to 2 digits
* Speed is number of 1.192755 Mhz PC timer clock ticks per clock transition
  period. So value here =  1 / (speed in Kbits/sec * 0.000001676) approx. 
* "Interface HW VCC enable" can be used as a power control / master signal
  inhibit line to target device (It switches on and off again 0.5 seconds
  before and after device access). Ignore it if isn't required.
* "Default port value" allows you fix any bits high on the parallel port
  that may be required by the hardware interface.
* A copy of the default spicfg.txt file is pasted below.


SPI Protocol notes:
-------------------

Mode 3 used: SPI Clock normally high.
Device latches data on rising clock
Data is shifted out of device on falling edge of clock.
Bit order: MSB to LSB

----------------------------------------------------------------------------
SPILEP.EXE directly accesses the parallel and timer ports so run it from
REAL MODE DOS only! (EG: make a boot disk in Windows)
----------------------------------------------------------------------------

Default spicfg.txt:-
--------------------

# ParPort = $0378	; Parallel port address		

* Parallel Port register's bit assignments / polarity (0) = Normal polarity, (1) bit is inverted

$00 (0)			; SPI clk port bit 
$01 (0)			; SPI data in port bit
$02 (0)			; SPI /cs port bit
$03 (0)			; Interface HW VCC enable
$06 (1)			; SPI data out port bit - read from ParPort+1

^ Default port = $10	; byte to write to parallel port at program start

& Speed = $000c		; number of PC timer ticks per half an SPI clock cycle

% ID list:

$10 = $0200 "128KB"	; ID / number of 256-byte pages / ascii size in quotes (5 chars max)
$11 = $0400 "256KB" 
$12 = $0800 "512KB" 
$13 = $1000 "1MB"

-
