//
//
// Title : SPI_Master_tb
// Design : SPI
// Author :
// Company :
//
//
//
// File : SPI_Master_TB. v
// Generated : Wed May 9 22:14:23 2012
// From : c:\My_Designs\SPI\SPI\src\TestBench\SPI_Master_TB_settings. txt
// By : tb_verilog. pl ver. ver 1.2s
//
//
//
// Description :
//
//
`timescale 1ns / 1ns
module SPI_Master_tb;

//Internal signals declarations:
tri [7:0]data_bus_bidir;
reg [7:0]data_bus;
//Continous assignment for inout port "data_bus".

assign data_bus_bidir = data_bus;
reg pro_clk;
reg miso;
reg [1:0]addr;
reg CS;
reg WR;

reg RD;
wire mosi;
wire sclk;

wire [7:0]ss;
// Unit Under Test port map

SPI_Master UUT (
.data_bus(data_bus_bidir),
.pro_clk(pro_clk),
.miso(miso),
.addr(addr),
.CS(CS),
.WR(WR),
.RD(RD),
.mosi(mosi),
.sclk(sclk),
.ss(ss));

always
begin
#5 pro_clk = ~pro_clk;
end

initial
$monitor($realtime,,"ps %h %h %h %h %h %h %h %h %h %h ",data_bus_bidir, pro_clk, miso, addr, CS, WR, RD, mosi, sclk, ss, control);
initial begin

end
initial begin

pro_clk =0;
data_bus=8'b;
addr=2'b00;
CS=1;
WR=1;
RD=0;
miso=1;
#30 WR=0;
data_bus=8'b;
addr=2'b10;
#500 WR=0;
data_bus=8'b;
#5 WR=1;
#500 WR=0;
addr=2'b11;
#5 RD=1;
end
endmodule