;
;             "hard_ffly2.txt" ;    
;
;       RAMEND
;  
;    ,   
;
    .cseg
;     .org (irq_res+int_vectors_size) ;    
	init:                    ;   
	   wdr ;   WDT
	   ldi tmp0,(1<<WDIF | 1<<WDCE | 1<<WDE)
     clr tmp1
     out WDTCR,tmp0
     out WDTCR,tmp1 ;   WDT 
     sbi ACSR,ACD ;  
     ldi tmp0,(1<<PRUSI | 1<<PRTIM1 | 1<<PRADC)
     out PRR,tmp0 ; USI=off, TIM1=off, ADC=off
;---------------------------------------------------
     ldi tmp0,1<<PUD ; MCUCR.PUD=1     
;     ttp223    , 
;   
     out MCUCR,tmp0
;---------------------------------------------------
;   /
; PB1 = ,  = 
     ldi tmp0,~(1<<out_line | 1<<pwr_set)
     out PORTB,tmp0 ; out_line = 0 for WS2812 compatibles,
           ;   
     ldi tmp0,(1<<out_line | 1<<pwr_set) ; com tmp0
     out DDRB,tmp0 ;  
;---------------------------------------------------
;  PLL    
; ( ,    
;  -)
;  PLL
;   ldi tmp0,1<<PLLE
;   out PLLCSR,tmp0
;   ldi tmp0,1<<PSR1
;   mov tmp1,tmp0 
;---------------------------------------------------
;     PLL (  16/8=2)
 wait_plock:
   in tmp0,PLLCSR
   sbrs tmp0,PLOCK
   rjmp wait_plock ;   -
;---------------------------------------------------
;    system clock 16 (PCK=64)
   rcall max_sys_clk
;---------------------------------------------------
;
;     PCK
; (  PLL   )
;
;   sbr tmp0,1<<PCKE
;   out PLLCSR,tmp0
;-----------------------------------------
;    T/C0   
;
 config_t0_mark:
    stop_tc0 ;   0  
     clr tmp0
     out TCNT0,tmp0
     out TIFR,tmp0
     out TCCR0B,tmp0 ;   
     ldi tmp0,dev_tl
     out OCR0A,tmp0 ;    OCR0A (0,004S)
     ldi tmp0,hard_th ;
     out TCCR0A,tmp0
     in tmp0,TIMSK
     sbr tmp0,(1<<OCIE0A)
     out TIMSK,tmp0 ;    OCF0A (OCIE0A=1)
     ldi tmp0,dev_ts
     sts cnt_tgrd,tmp0 ;    cnt_tgrd  dev_th(0,1S)
     sei ;  
     ldi tmp0,t0_on ;   
     out TCCR0B,tmp0
;---------------------------------------------------
;    
     sbi port_out,pwr_set
     ser tmp0
 wait_key:
       dec tmp0
       brne wait_key
;---------------------------------------------------
;