//==============================================================
//
//	Program:        Radar.c
//
//	Created:    14.10.2004
//
//	Author:     Alexander Rakhmatulin
//
//==============================================================

// 	LED segments a-g are at PD0 - PD7, and
// 	the catodes are at PC2 - PC5

#include <avr/signal.h>		// include "signal" names 
#include <avr/interrupt.h>	// include interrupt support
#include <avr/io.h>
//#include <inttypes.h>
#include <avr/pgmspace.h>	//	     	
#include <avr/delay.h>

#include "global.h"			//	   AVRLIB	
#include "Radar.h"  //     
//

unsigned char blanc ;	//   -   

unsigned char digits[] = {zero,one,two,three,four,five,six,seven,eight,nine,
a_hex,b_hex,c_hex,d_hex,e_hex,f_hex};

volatile unsigned char k=0;	//Digits 
unsigned char i=0;  //     

volatile unsigned char buf1,buf2,buf3,buf4;

volatile unsigned int n;
volatile unsigned char kcycle; // 

volatile unsigned int timer_val;
//   

volatile unsigned char prescaler_val;
//   

volatile unsigned int res0=0,res1=0,res2=0,res3=0;

//=============================================================
//
// signal handler for tcnt0 overflow interrupt
//
//============================================================= 
SIGNAL(SIG_OVERFLOW0)        
{
 /* preset counter to get this interrupt again */
	TCNT0 = 0x16; 
//	kcycle = kcycle + 1;
//======    40000   ==================	
if (n == 1)
	{				
	UltraSoundPort &= ~(1 << UltraSoundOut1);	//
	UltraSoundPort |= (1 << UltraSoundOut2);
	n = 0;
	}
else 
	{
	UltraSoundPort |= (1 << UltraSoundOut1);		//
	UltraSoundPort &= ~(1 << UltraSoundOut2);	
	n = 1;
	}
//==============================================================
 //*********************************************************
//		   
//				 
//*********************************************************

	buf1 = digits[res0];
	buf2 = digits[res1];
	buf3 = digits[res0]| SEG_dot;
	buf4 = digits[res1] ;

//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//		    
//		    
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//switch(k)
//	{
//	case (0):
//		{
//		CATOD_PORT &= ~((1 << CATOD1)|(1 << CATOD2)|(1 << CATOD3)|(1 << CATOD5));
//		CATOD_PORT2 &= ~(1 << CATOD4);
//		//	All catodes off
//		SEG_PORT = buf4;				//	Set segments
//		CATOD_PORT |= (1 << CATOD1);	//	One catode on
//		}
//	break;

//	case (1): 
//		{
//		CATOD_PORT &= ~((1 << CATOD1)|(1 << CATOD2)|(1 << CATOD3)|(1 << CATOD5));
//		CATOD_PORT2 &= ~(1 << CATOD4);		
//		SEG_PORT = buf3;	
//		CATOD_PORT |= (1 << CATOD2);
//		}
//	break;

//	case (2): 
//		{
//		CATOD_PORT &= ~((1 << CATOD1)|(1 << CATOD2)|(1 << CATOD3)|(1 << CATOD5));
//		CATOD_PORT2 &= ~(1 << CATOD4);		
//		SEG_PORT = buf2;	
//		CATOD_PORT |= (1 << CATOD3);
//		}
//	break;

//	case (3):
//		{
//		CATOD_PORT &=  ~((1 << CATOD1)|(1 << CATOD2)|(1 << CATOD3)|(1 << CATOD5));
//		CATOD_PORT2 &= ~(1 << CATOD4);		
//		SEG_PORT = buf1;		
//		CATOD_PORT2 |= (1 << CATOD4);
//		}				
//	break;
//	}	
//$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
//			
//$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
	if (k>0 )
	{k--;
	}	
	else
	{	
		k=3;	
	}
}
//$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$

//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//		     
//					/ 1
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

SIGNAL(SIG_OVERFLOW1)
{

}

//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//		     
//					/ 2
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SIGNAL(SIG_OVERFLOW2)
{
	// set TCNT2 
TCNT2 = 0xdb;	//   80000 

//======    40000   ==================	
if (n == 1)
	{				
	UltraSoundPort &= ~(1 << UltraSoundOut1);	//
	UltraSoundPort |= (1 << UltraSoundOut2);
	n = 0;
	}
else 
	{
	UltraSoundPort |= (1 << UltraSoundOut1);		//
	UltraSoundPort &= ~(1 << UltraSoundOut2);	
	n = 1;
	}
//==============================================================
}

//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//		     
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SIGNAL(SIG_COMPARATOR)
{

}

// External Interrupt 0 service routine (used to initiate UART3 receive)
SIGNAL(SIG_INTERRUPT0)
{

}
//HEXTOBCD-HEXTOBCD-HEXTOBCD-HEXTOBCD-HEXTOBCD-HEXTOBCD-HEX
//
//	   
//
//HEXTOBCD-HEXTOBCD-HEXTOBCD-HEXTOBCD-HEXTOBCD-HEXTOBCD-HEX
void hex_to_bcd(unsigned int bc)
{

}

//.............................................................//
//	 7-      
//	:  
//.............................................................//

int main(void)
{
//	CATOD_DDR_PORT |= (1 << CATOD1)|(1 << CATOD2)|(1 << CATOD3)|(1 << CATOD5);
//	CATOD_DDR_PORT2 |= (1 << CATOD4);
	//	    

//	CATOD_PORT &= ~((1 << CATOD1)|(1 << CATOD2)|(1 << CATOD3)|(1 << CATOD5));
//	CATOD_DDR_PORT2 &= ~(1 << CATOD4);	
	//	  ,    0
//
//	SEG_DDR_PORT = 0xff;
	//	    

	UltraSoundPortDDR |= (1 << UltraSoundOut1)|(1 << UltraSoundOut2);
	UltraSoundPort &= ~((1 << UltraSoundOut1)|(1 << UltraSoundOut2));
	
	ComparatorDDR &= ~(1 << Comparator1);   //set AIN1 as input
	ComparatorPort &= ~(1 << Comparator1);	//remove pullup
	
//	ACSR |= (1<<ACBG)|(1<<ACIC)|(1<<ACO);	//    (1<<ACO)
//	ACSR &= ~((1<<ACD));

//	ACSR |= (1<<ACBG)|(1<<ACIC)|(1<<ACO)|(1<<ACIE)|(1<<ACIS0)|(1<<ACIS1);
//		   

//	Bit 7  ACD: Analog Comparator Disable
//	When this bit is written logic one, the power 
//	to the Analog Comparator is switched off.
//
//	Bit 6  ACBG: Analog Comparator Bandgap Select
//	When this bit is set, a fixed bandgap reference voltage
//	replaces the positive input to the Analog Comparator.
//	When this bit is cleared, AIN0 is applied to the positive 
//	input of the Analog Comparator. 
//
//	Bit 5  ACO: Analog Comparator Output
//	The output of the Analog Comparator is synchronized and then
//	directly connected to ACO. The synchronization introduces
//	a delay of 1 - 2 clock cycles.
//
//	Bit 4  ACI: Analog Comparator Interrupt Flag
//	This bit is set by hardware when a comparator output event
//	triggers the interrupt mode defined by ACIS1 and ACIS0.
//
//	Bit 3  ACIE: Analog Comparator Interrupt Enable
//	When written logic zero, the interrupt is disabled.
//
//	Bit 2  ACIC: Analog Comparator Input Capture Enable
//	When written logic one, this bit enables the Input Capture
//	function in Timer/Counter1 to be triggered by 
//	the Analog Comparator.
//
//	Bits 1,0  ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
//	ACIS1 ACIS0 Interrupt Mode
//	0		0	Comparator Interrupt on Output Toggle
//	0		1	Reserved
//	1		0	Comparator Interrupt on Falling Output Edge
//	1		1	Comparator Interrupt on Rising Output Edge
//
//---- cmp ---- cmp ---- cmp ---- cmp ---- cmp ---- cmp ---- end
	
 	TIMSK |= (1<<TOIE0)|(1<<TOIE2);	
	/* enable TCNT0, TOIE2 overflow */
	
//   /
	TCNT0 = 0x16;				// preset TCNT0 0x16 f=100Hz 
    TCCR0 = TIMER2_CLK_DIV256;	// count with cpu clock/256
 
//
	TCNT2 = TCNT2 = 0xdb;		//   80000 
    TCCR2 |= TIMER2_CLK_DIV1;	// count with cpu clock/1

//       
//   -     
//  
	hex_to_bcd(n);

//   
 sei();

//   
	while (1)
	{

	}
}
