.CSEG
.ORG $000 ; (RESET)
RJMP Reset
.ORG $001
RETI ; (INT0) External Interrupt Request 0
.ORG $002
RETI ; (INT1) External Interrupt Request 1
.ORG $003
RETI ; (TIMER2 COMP) Timer/Counter2 Compare Match
.ORG $004
rjmp Timer2 ; (TIMER2 OVF) Timer/Counter2 Overflow
.ORG $005
RETI ; (TIMER1 CAPT) Timer/Counter1 Capture Event
.ORG $006
RETI ; (TIMER1 COMPA) Timer/Counter1 Compare Match A
.ORG $007
RETI ; (TIMER1 COMPB) Timer/Counter1 Compare Match B
.ORG $008
RETI ; (TIMER1 OVF) Timer/Counter1 Overflow
.ORG $009
RETI ; (TIMER0 OVF) Timer/Counter0 Overflow
.ORG $00A
RETI ; (SPI,STC) Serial Transfer Complete
.ORG $00B
RETI ; (USART,RXC) USART, Rx Complete
.ORG $00C
RETI ; (USART,UDRE) USART Data Register Empty
.ORG $00D
RETI ; (USART,TXC) USART, Tx Complete
.ORG $00E
RJMP ADC_OK ; (ADC) ADC Conversion Complete
.ORG $00F
RETI ; (EE_RDY) EEPROM Ready
.ORG $010
RETI ; (ANA_COMP) Analog Comparator
.ORG $011
RJMP TWSI ; (TWI) 2-wire Serial Interface
.ORG $012
RETI ; SPM_RDY Store Program Memory Ready
.ORG INT_VECTORS_SIZE ; Конец таблицы прерываний


Reset:
LDI R16,Low(RAMEND)
OUT SPL,R16
LDI R16,High(RAMEND)
OUT SPH,R16
.def Temp1=R17
.def ADC_data1=R18
.def ADC_data2=R19
ldi R21, 0
ldi R20, 6
ldi R16, 255
OUT DDRB, R16

ldi R16, 0b00000111
OUT TCCR2, R16
ldi R16, 0b10000000
OUT TIMSK, R16
ldi R16, 0b00001000
OUT ASSR, R16

ldi R16, 0b01000000
OUT ADMUX,R16

ldi R16, 0b11101111
OUT ADCSRA, R16

ldi R16, 2
OUT TWBR, R16
SEI
RETI

Main:
rjmp Main

ADC_OK:
cli
IN ADC_data1,ADCL
IN ADC_data2,ADCH
ldi R17, 0
Reload:
mul R18,R20
movw R22,R0
mul R19,R21
movw R24,R0
mul R19,R20
clr R19
add R23,R0
adc R24,R1
adc R25,R19
mul R18,R21
add R23,R0
adc R24,R1
adc R25,R19
nop
nop
nop
ldi R24, 0
ldi R25, 0
dec r17
CPI R17, 2
BRNE Reload


D1:
ldi r16,0b11101000
ldi r17, 0b00000011
mov r22,r14
mov r23, r15

return1000:
inc R9
sub R22,R16
sbc R23,R17
BRPL return1000
dec r9


D2:
ldi r16,0b01100100
ldi r17, 0b00000000

return100:
inc r10
sub R22, R16
sbc R23, R17
BRPL return100
dec r10

D3:
ldi r16,0b00001010
ldi r17, 0b00000000

return10:
inc r11
sub R22,R16
sbc R23,R17
BRPL return10
dec r11

mov r12, r23

inc R29
CPI R29, 2
BREQ Load
ldi R16, 0b01000000
OUT ADMUX,R16
sei
reti

Timer2:
cli
rcall TWI_Start
sei
reti



TWSI:

cli
in r16,TWSR
nop
nop
inc R28
cpi R28, 1
breq rl1
cpi R28, 2
breq rl2
cpi R28, 3
breq rl3
cpi R28, 4
breq rl4

andi r16, 0xF8
cpi r16, 0x08
breq SLAW_Adr
cpi r16, 0x28
breq ByteTransmit
cpi r16, 0x58
breq Stopp

Vix:
sei
reti

ByteTransmit:
inc r30
cpi r30, 5
breq TWI_Stop
mov r16, r27
rcall TWI_SendByte
rjmp Vix

Stopp:
in r19, TWDR
nop
nop
rcall TWI_Stop
rjmp Vix

SLAW_Adr:
ldi r16, 0b00000000
rcall TWI_SendByte
rjmp Vix

TWI_Start:
ldi r16, 0b10100101
out TWCR, r16
ret

TWI_Stop:
ldi r16, 0b00010100
out TWCR, r17
ret

TWI_SendByte:
out TWDR, r16
ldi r16, 0b10000101
out TWCR, r16
ret

rl1:
mov r27, r9
ret

rl2:
mov r27, r10
ret

rl3:
mov r27, r11
ret

rl4:
mov r27, r12
ldi R28, 0
ret

Load:
ldi R16, 0b01000001
OUT ADMUX,R16
Ldi R29, 0
Ret