/**
 ******************************************************************************
 * @file           : main.c
 * @author         : Auto-generated by STM32CubeIDE
 * @brief          : Main program body
 ******************************************************************************
 * @attention
 *
 * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.
 * All rights reserved.</center></h2>
 *
 * This software component is licensed by ST under BSD 3-Clause license,
 * the "License"; You may not use this file except in compliance with the
 * License. You may obtain a copy of the License at:
 *                        opensource.org/licenses/BSD-3-Clause
 *
 ******************************************************************************
 */

#include "main.h"
   volatile unsigned int   bufer;
     volatile unsigned int   bufer1;
static uint16_t pauza=0;
volatile unsigned int adc_data=0;
 void NMI_Handler(void)
{
  if((RCC->CIR & RCC_CIR_CSSF) != 0) // HSE fail
  {
    RCC->CIR |= RCC_CIR_CSSC; // Clear CSSF flag

  }
}
 void DMA2_Stream0_IRQHandler (void)
{
	 if(DMA2->LISR &DMA_LISR_TCIF0)
	 {
		 DMA2->LIFCR |= DMA_LIFCR_CTCIF0;

		 bufer1 = ADC1->DR;
				 if(bufer1>595)
				 {
					 GPIOC-> BSRR |=GPIO_BSRR_BS13;
				 }
				 else
				 {
					 GPIOC-> BSRR |=GPIO_BSRR_BR13;
				 }
	 }
      if(DMA2->LISR &DMA_LISR_TEIF0)
	 {
		 DMA2->LIFCR |= DMA_LIFCR_CTEIF0;
	 }
 //if( DMA2)
}
void TIM4_IRQHandler (void)
{
	if(TIM4->SR & TIM_SR_UIF)
	{
		TIM4->SR &= ~ TIM_SR_UIF;
		//IWDG->KR = 0xAAAA;
		pauza++;
		        if(pauza>20)
				{
					//GPIOC->BSRR |= GPIO_BSRR_BS1;
					//GPIOC-> BSRR |=GPIO_BSRR_BS13;
				}
				if(pauza>40)
				{

					// GPIOC-> BSRR |=GPIO_BSRR_BR13;
					// GPIOD->BSRR |= GPIO_BSRR_BR1;
							pauza=0;
				}


	}
}
  void RCC_init(void)
{
	FLASH->ACR |= FLASH_ACR_PRFTEN ;
		//FLASH->ACR &=~ (FLASH_ACR_LATENCY_2WS) ;
	FLASH->ACR |= FLASH_ACR_LATENCY_3WS ;

	//PWR->CR|= PWR_CR_VOS;
	RCC->CR|=RCC_CR_HSEON;											// Enable HSE
    while (!(RCC->CR & RCC_CR_HSERDY));


    RCC->CR|=RCC_CR_CSSON;

	 RCC->PLLCFGR |=RCC_PLLCFGR_PLLSRC_HSE  ;
	    RCC->PLLCFGR |=_VAL2FLD(RCC_PLLCFGR_PLLM,4);

	    RCC->PLLCFGR |=_VAL2FLD(RCC_PLLCFGR_PLLN,168);

	     RCC->PLLCFGR&=~RCC_PLLCFGR_PLLP_0 ;
	     RCC->PLLCFGR&=~RCC_PLLCFGR_PLLP_1 ;
	     RCC->CFGR |= RCC_CFGR_HPRE_DIV1;//	��������� ����  AHB
	   			        RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;//	��������� ����  APB1

	   				   RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;

			RCC->CR |= RCC_CR_PLLON;                      							// enable PLL
			while(!(RCC->CR & RCC_CR_PLLRDY))
			{

			}

		    RCC->CFGR |= RCC_CFGR_SW_PLL;                 							// select source SYSCLK = PLL
			while(!(RCC->CFGR&  RCC_CFGR_SWS_PLL))

				{

				}



}
 void init_IWDGtimer(void)
 {
 	RCC->CSR|= RCC_CSR_LSION;



 	   IWDG->KR = 0x5555; // Access to registers
 	   IWDG->PR&= ~(IWDG_PR_PR_0 | IWDG_PR_PR_1 | IWDG_PR_PR_2); // 4096
 	   IWDG->RLR =  2000;//0x7FF;
 	   while (!((IWDG->SR & IWDG_SR_PVU) && (IWDG->SR & IWDG_SR_RVU))){} // wait while bist of PVU and RVU will be set.
 	   IWDG->KR = 0xCCCC; // Start count down;
 }
 void adc_init(void)
 {
	  GPIOA->MODER |= GPIO_MODER_MODER1;
	  GPIOA->MODER |= GPIO_MODER_MODER2;

 		  RCC->APB2ENR|=RCC_APB2ENR_ADC1EN;
 		  ADC1->CR2 &=~ADC_CR2_CONT;//�������� ���
 		  	 //ADC1->CR2=ADC_CR2_EXTSEL;
 		     	 ADC1->CR2 |=ADC_CR2_EXTEN;
 		  ADC1->SMPR2 &=~ ADC_SMPR2_SMP1_0; //1
 		 ADC1->SMPR2&=~ADC_SMPR2_SMP1_1; //1
 		  ADC1->SMPR2 &=~ ADC_SMPR2_SMP1_2; //1


 		 // ADC1->JSQR|=ADC_JSQR_JSQ1_0;;

 		     ADC1->SQR3   |=ADC_SQR3_SQ1_0;   //1 IN1
 		  	  ADC1->SQR3   &= ~ ADC_SQR3_SQ1_1;     //0
 		  	  ADC1->SQR3   &= ~ADC_SQR3_SQ1_2;   //0
 		  	  ADC1->SQR3   &=~  ADC_SQR3_SQ1_3;     //0
 		  	  ADC1->SQR3   &= ~ADC_SQR3_SQ1_4;
 		  	  ADC1->CR2|=ADC_CR2_DMA;
 		 	 ADC1->CR2 |=  ADC_CR2_ADON;
 		 	//ADC3->CR2|=ADC_CR2_EXTSEL_2 |ADC_CR2_EXTSEL_1;
 		 	//ADC1->CR2 |= ADC_CR2_SWSTART;
 }
 void DMA1_init(void)
 {

 	RCC->AHB1ENR|= RCC_AHB1ENR_DMA1EN;
 	//DMA1_Stream0->CR = 0;
 	DMA1_Stream0->M0AR |=(uint32_t)& bufer;
 	DMA1_Stream0->PAR |=(uint32_t)&TIM4->CCR1 ;
 	DMA1_Stream0->NDTR = 2;
 	DMA1_Stream0->CR&= ~DMA_SxCR_PINC;
 	DMA1_Stream0->CR&= ~DMA_SxCR_MINC;
 	DMA1_Stream0->CR|= DMA_SxCR_PSIZE_0;
 	DMA1_Stream0->CR|= DMA_SxCR_MSIZE_0;

 	       DMA1_Stream0->CR|=DMA_SxCR_CHSEL_0;
 	       DMA1_Stream0->CR|= DMA_SxCR_CHSEL_1;
 	       DMA1_Stream0->CR&=~ DMA_SxCR_CHSEL_2 ;
 	       DMA1_Stream0->CR&=~ DMA_SxCR_PFCTRL;//DMA ma
 	             DMA1_Stream0->CR|= DMA_SxCR_PL; //DMA ma
 	             DMA1_Stream0->FCR|=DMA_SxFCR_DMDIS;//��������� fIFO
 	             DMA1_Stream0->CR|= DMA_SxCR_DIR_0;
 	             DMA1_Stream0->CR|= DMA_SxCR_CIRC;
 	             DMA1_Stream0->CR|= DMA_SxCR_EN;//��
 }
 void DMA2_init(void)
  {

       RCC->AHB1ENR|= RCC_AHB1ENR_DMA2EN;
       DMA2_Stream0->CR = 0;

       DMA2_Stream0->PAR |=(uint32_t)& ADC1->DR;
        DMA2_Stream0->M0AR |=(uint32_t)& bufer1;
      //  TIM4->CCR1= bufer;
        DMA2_Stream0->NDTR = 1;

        DMA2_Stream0->CR&= ~DMA_SxCR_PINC;
        DMA2_Stream0->CR&= ~DMA_SxCR_MINC;
        DMA2_Stream0->CR|= DMA_SxCR_PSIZE_0;
        DMA2_Stream0->CR|= DMA_SxCR_MSIZE_0;
        DMA2_Stream0->CR&=~ DMA_SxCR_CHSEL_0 ;
        DMA2_Stream0->CR&=~ DMA_SxCR_CHSEL_1;
        DMA2_Stream0->CR&=~ DMA_SxCR_CHSEL_2 ;
      DMA2_Stream0->CR&=~ DMA_SxCR_PFCTRL;//DMA ma
        DMA2_Stream0->CR|= DMA_SxCR_PL; //DMA ma
        //DMA2_Stream0->FCR|=DMA_SxFCR_DMDIS;//��������� fIFO
        DMA2_Stream0->CR&=~ DMA_SxCR_DIR;
        DMA2_Stream0->CR|= DMA_SxCR_CIRC;
        DMA2_Stream0->CR|=DMA_SxCR_TCIE;
        DMA2_Stream0->CR|=DMA_SxCR_TEIE;
        //DMA2_Stream0->CR|=DMA_SxCR_DMEIE;
        DMA2_Stream0->CR|= DMA_SxCR_EN;//���   DMA2_Stream0
        NVIC_EnableIRQ(DMA2_Stream0_IRQn);
        //ADC1->CR2|=ADC_CR2_DMA;

  }
 static void AHB1ER_init(void)
{
	RCC->AHB1ENR|=RCC_AHB1ENR_GPIOAEN;
	RCC->AHB1ENR|=RCC_AHB1ENR_GPIOBEN;
	RCC->AHB1ENR|=RCC_AHB1ENR_GPIOCEN;
	RCC->AHB1ENR|=RCC_AHB1ENR_GPIODEN;
}
 static void GPIO_init(void)
{
	                    GPIOC->MODER &=~ GPIO_MODER_MODER13_1;
				 	  GPIOC->MODER |= GPIO_MODER_MODER13_0;
				 	 // GPIOC ->OTYPER |=GPIO_OTYPER_OT13;
				 	  //���0 ���������� �������� ������ GPIO
				 	   GPIOC->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR13_1; //���1
				 	   GPIOC->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR13_0;
				 	  GPIOC->PUPDR |=GPIO_PUPDR_PUPDR13_1;
				 	    GPIOC->PUPDR &=~ GPIO_PUPDR_PUPDR13_0;
				 	    GPIOC->MODER &=~ GPIO_MODER_MODER13_1;

				 					 	  GPIOC->MODER |= GPIO_MODER_MODER0_0;
				 					 	 // GPIOC ->OTYPER |=GPIO_OTYPER_OT13;
				 					 	  //���0 ���������� �������� ������ GPIO
				 					 	   GPIOC->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR0_1; //���1
				 					 	   GPIOC->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR0_0;
				 					 	  GPIOC->PUPDR |=GPIO_PUPDR_PUPDR0_1;
				 					 	    GPIOC->PUPDR &=~ GPIO_PUPDR_PUPDR0_0;
}
 void timer2_init(void)
 {


 	  RCC->APB1ENR |=RCC_APB1ENR_TIM2EN;

 	   TIM2->PSC=9; // ����������� �������� ��� ������ ����� 1000 ��� � �������
 	   	TIM2->ARR  = 7000;

          TIM2->CR2|=TIM_CR2_MMS_1;//бит управлени ацп

 	    TIM2->EGR = TIM_EGR_UG ;



 	     TIM2->CR1|= TIM_CR1_CEN;

 }
 static void timer4_init(void)
{
	RCC->APB1ENR|=RCC_APB1ENR_TIM4EN;
			TIM4->PSC=3500-1;
			 TIM4->ARR=100-1;
			// TIM4->EGR|= TIM_EGR_UG;
			 TIM4->DIER = TIM_DIER_UIE;
				TIM4->CR1=  TIM_CR1_CEN;
				 NVIC_EnableIRQ(TIM4_IRQn);
}

int main(void)
{
 	RCC_init();

	AHB1ER_init();
	GPIO_init();
	timer2_init();
	timer4_init();
	adc_init();
	DMA2_init();

	//ADC1->CR2 |= ADC_CR2_SWSTART;
		ADC1->CR2|=ADC_CR2_EXTSEL_2 |ADC_CR2_EXTSEL_1;
	while(1)
	{
		//ADC1->CR2 |= ADC_CR2_SWSTART;
	//	ADC1->CR2|=ADC_CR2_EXTSEL_2 |ADC_CR2_EXTSEL_1;
	//	while(!(ADC1->SR & ADC_SR_EOC));
	//	 ADC1->SR &=~ ADC_SR_EOC;
	//	 adc_data = ADC1->DR;
	//	 if(adc_data>595)
	//	 {
	//		 GPIOC-> BSRR |=GPIO_BSRR_BS13;
	//	 }
	//	 else
	//	 {
			// GPIOC-> BSRR |=GPIO_BSRR_BR13;
	//	 }
		//GPIOC-> BSRR |=GPIO_BSRR_BS13;
	}
}