/*
 * main.c
 *
 *  Created on: 20 ���. 2020 �.
 *      Author: Ivan
 */
#include "main.h"
#include "stm32f103xb.h"
#include "stm32f1xx.h"
#define SYSCLOCK 8000000U
//#define start_converADC2 ADC
volatile unsigned int adc_data1=0;
volatile unsigned int adc_data2=0;
volatile unsigned int pauza=0;
__IO uint32_t tmpreg;
__IO uint32_t SysTick_CNT = 0;
  //int bufer=TIM4->CCR1*16;
void pauzat (int T)//���� ����� �����(���������) ��� �������� �������� � ���������� #include "paua.h"����� ������ � �������� ����� pauza()� ������ ����� ���������� T
{
   int i=0;//�������� ��������������� i
   char t=0;// �������� ������������ ���������� t ������� ����� ���������������
   for(i=0;i<T;t++) //���������� � �����
  {
	if(t==255)i=i+1;// ������� ������ ����� ����� ����������� i ������������ ��������� TCCR2 ������������ 0.1.2 ������ ��� ��������� ������� ������ �������
  }
}
void ADC1_2_IRQHandler(void)
{

	 //    ADC1->SR &=~ ADC_SR_EOC;
	 //    ADC2->SR &=~ ADC_SR_EOC;
	  //   ADC1->DR=ADC_DR_DATA ;
	 //    adc_data1 = ADC1->DR  ;
	 //    TIM4->CCR1=adc_data1*16;


	    // ADC2->DR=ADC_DR_ADC2DATA ;
	    //  adc_data2 =ADC2->DR;



	     // TIM4->CCR2=adc_data2*16;



}

void TIM1_UP_IRQHandler(void)
{
  TIM1->SR &= ~ TIM_SR_UIF;
  IWDG->KR = 0xAAAA;
  pauza++;
  if(pauza>10)
  {
	  GPIOC->ODR|=GPIO_ODR_ODR13 ;
  }
  if(pauza>20)
  {
	  GPIOC->ODR&=~GPIO_ODR_ODR13 ;
	  pauza=0;
  }
}
void tx_uart(char data)
{
	while (!(USART1->SR & USART_SR_TC));                     // ���� ���� ��� TC � �������� SR ������ 1
	   USART1->DR=data;

}
void delay(__IO uint32_t tck)
{
 while(tck)
 {
   tck--;
 }
}
void delay_ms(uint32_t ms)
{
	MODIFY_REG(SysTick->VAL,SysTick_VAL_CURRENT_Msk,SYSCLOCK / 1000 - 1);

  SysTick_CNT = ms;
  while(SysTick_CNT) {}
}
void NMI_Handler(void)
{
	 if((RCC->CIR & RCC_CIR_CSSF) != 0) // HSE fail
	  {
	    RCC->CIR |= RCC_CIR_CSSC; // Clear CSSF flag

	  }
}
void init_systimer(void)
{
	 MODIFY_REG(SysTick->LOAD,SysTick_LOAD_RELOAD_Msk,SYSCLOCK / 1000 - 1);


  CLEAR_BIT(SysTick->VAL, SysTick_VAL_CURRENT_Msk);
    SET_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_TICKINT_Msk);

}
void RCC_init(void)
{
	FLASH->ACR |=FLASH_ACR_PRFTBE ;
		FLASH->ACR|=FLASH_ACR_LATENCY_2;

		RCC->CR  |=RCC_CR_HSEON ;
		while(!(RCC->CR&RCC_CR_HSERDY ))
		{

		}
	    RCC->CR |=RCC_CR_CSSON ;
	    RCC->CFGR|=RCC_CFGR_PLLMULL9;
	    RCC->CFGR|=RCC_CFGR_HPRE_DIV1; //_VAL2FLD(RCC_CFGR_HPRE,1);
	   	          RCC->CFGR|=RCC_CFGR_PPRE1_DIV1 ;//_VAL2FLD(RCC_CFGR_PPRE1,2);
	   	          RCC->CFGR|=RCC_CFGR_PPRE2_DIV1; //_VAL2FLD(RCC_CFGR_PPRE2,1);
	   	          RCC->CFGR|= RCC_CFGR_ADCPRE_DIV2;
	    RCC->CFGR|=RCC_CFGR_PLLSRC;
	    RCC->CFGR|=RCC_CFGR_PLLXTPRE_HSE;



	     RCC->CR|=RCC_CR_PLLON;
	     while(!(RCC->CR&RCC_CR_PLLRDY))
	     {

	     }

	       RCC->CFGR|=RCC_CFGR_SW_PLL;
	       while((RCC->CFGR & RCC_CFGR_SWS) !=RCC_CFGR_SWS_PLL ) {}
}
void RCC_DeInit(void)
{
  SET_BIT(RCC->CR, RCC_CR_HSION);
  while(READ_BIT(RCC->CR, RCC_CR_HSIRDY == RESET)) {}
  MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, 0x80U);
  CLEAR_REG(RCC->CFGR);
  while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) {}
  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
  while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) {}
  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON);
  while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) {}
  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
  //Reset all CSR flags
  SET_BIT(RCC->CSR, RCC_CSR_RMVF);
}
void SetSysClockTo72(void)
{
  SET_BIT(RCC->CR, RCC_CR_HSEON);
  while(READ_BIT(RCC->CR, RCC_CR_HSERDY == RESET)) {}
  //Enable the Prefetch Buffer
  CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
  SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, FLASH_ACR_LATENCY_2);
  MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_CFGR_HPRE_DIV1);
  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_CFGR_PPRE2_DIV1);
  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_CFGR_PPRE1_DIV2);
  MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL,
             RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL9);
  SET_BIT(RCC->CR, RCC_CR_PLLON);
  while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != (RCC_CR_PLLRDY)) {}
  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_CFGR_SW_PLL);
  while(READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
}
void sys_timer_init(void)
{

}

void GPIOC_init(void)
{
	RCC->APB2ENR|=RCC_APB2ENR_IOPCEN;
   GPIOC->CRH&=~GPIO_CRH_CNF13;
	GPIOC->CRH|= GPIO_CRH_MODE13_1;
}
void APB_init(void)
{
	RCC->APB1ENR|=RCC_APB2ENR_IOPAEN;
	RCC->APB2ENR|=RCC_APB2ENR_IOPBEN ;
	RCC->APB2ENR|=RCC_APB2ENR_IOPCEN;
	RCC->APB2ENR|=RCC_APB2ENR_AFIOEN;



}
void porta_inifs(void)
{
	//RCC->APB1ENR|=RCC_APB2ENR_IOPAEN;

}
void tx_uart2( char data)
{
	while ((USART2->SR & USART_SR_TXE) == 0) {}
   USART1->DR = data;

	//while (!(USART2->SR & USART_SR_TC ))
	//{

	//}
	//USART2->SR &=~ USART_SR_TC;// ���� ���� ��� TC � �������� SR ������ 1
  // USART2->DR=data;                                    // �������� ���� ����� UART
}
void tx_str1(char * string)
{
   uint8_t i=0;
  // int i=0;
   while (string[i])
   {
      tx_uart2(string[i]);
      i++;
     // tx_uart(string[i++]);
   }
}
void usart1_init(void)
{
	//SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);

	// RCC->APB2ENR|=RCC_APB2ENR_USART1EN;
	 RCC->APB2ENR|=RCC_APB2ENR_IOPAEN  ;
	//  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);
	  //Set GPIO_TX_RX
	  //SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);
	 // tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);
	  GPIOA->CRH|=GPIO_CRH_MODE10 | GPIO_CRH_CNF10_1 | GPIO_CRH_CNF9_0|GPIO_CRH_CNF10_0 | GPIO_CRH_MODE9 | GPIO_CRH_CNF9_1;
	// GPIOA->CRH|=GPIO_CRH_CNF9_1;
	//	 GPIOA->CRH&=~GPIO_CRH_CNF9_0;

	  // GPIOA->CRH|= GPIO_CRH_MODE9;
	  // GPIOA->CRH|=GPIO_CRH_CNF9_1;
	   //RCC->APB2ENR|=RCC_APB2ENR_AFIOEN;
	   	//	 GPIOA->CRH&=~GPIO_CRH_CNF10_0;
	   //	   GPIOA->CRH|= GPIO_CRH_MODE10_1;
	   //	   GPIOA->CRH|= GPIO_CRH_MODE10_0;
	  	//   AFIO->MAPR&=~AFIO_MAPR_USART1_REMAP ;
	  	 RCC->APB2ENR|=RCC_APB2ENR_USART1EN;
	  	  //USART1->CR1|=USART_CR1_M;
	  	 //  USART1->CR2&= ~USART_CR2_STOP;

	  //	  USART1->CR2=0;
	  //	USART1->CR3=0;
	  	//USART1->BRR =0x271 ;
	 // if(READ_BIT(USART1->CR1, USART_CR1_UE) != (USART_CR1_UE))
	  // {
	    MODIFY_REG(USART1->CR1,
	            USART_CR1_M | USART_CR1_PCE | USART_CR1_PS ,USART_CR1_TE |USART_CR1_RE);
	 //  }
	   //  USART1->CR1|=( USART_CR1_M | USART_CR1_PCE | USART_CR1_PS ,USART_CR1_TE |USART_CR1_RE);
	  	// CLEAR_BIT(USART1->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
	  	//  CLEAR_BIT(USART1->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
	  	USART1->BRR =0x271 ;
	  	//WRITE_REG(USART1->BRR,0x271);

		 USART1->CR1 |=USART_CR1_UE;                         // ��������� ���������� �� ������ ������
		// NVIC_EnableIRQ (USART1_IRQn);
}
static void USART1_Init(void)
{
  //USART Clock
  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);
  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);
  //Set GPIO_TX_RX
  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);
  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);
  MODIFY_REG(GPIOA->CRH, GPIO_CRH_MODE10 | GPIO_CRH_CNF10_1 | GPIO_CRH_CNF9_0,
                          GPIO_CRH_CNF10_0 | GPIO_CRH_MODE9 | GPIO_CRH_CNF9_1);
  ////USART needs to be in disabled state, in order to be able to configure some bits in CRx registers
  if(READ_BIT(USART1->CR1, USART_CR1_UE) != (USART_CR1_UE))
  {
    MODIFY_REG(USART1->CR1,
           USART_CR1_M | USART_CR1_PCE | USART_CR1_PS ,USART_CR1_TE |USART_CR1_RE);
  }
  //Async Mode
  CLEAR_BIT(USART1->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
  CLEAR_BIT(USART1->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
  //115200
  WRITE_REG(USART1->BRR,0x271); //((0x27)<<4)|0x01);
  //Enable
  SET_BIT(USART1->CR1, USART_CR1_UE);
}
void adc1_init(void)
{

	//	RCC->CFGR &=~ RCC_CFGR_ADCPRE;

	   // RCC->APB2ENR|=RCC_APB2ENR_IOPAEN;
		GPIOA->CRL&=~GPIO_CRL_CNF1;
	   	GPIOA->CRL&=~ GPIO_CRL_MODE1;
		GPIOA->CRL&=~GPIO_CRL_CNF2;
	    GPIOA->CRL&=~ GPIO_CRL_MODE2;
	    RCC->APB2ENR |=  RCC_APB2ENR_ADC1EN;
	    RCC->APB2ENR |=  RCC_APB2ENR_ADC2EN;

		//RCC->CFGR |= RCC_CFGR_ADCPRE_DIV2;

		//������ ������������ ���
		 ADC1->CR2 |= ADC_CR2_RSTCAL;
		 while (!(ADC1->CR2 & ADC_CR2_RSTCAL))
		 {
		 }

		 ADC1->CR2 |= ADC_CR2_CAL;
		// while (!(ADC1->CR2 & ADC_CR2_CAL));
		// {
		// }

		 ADC1->CR2 |=ADC_CR2_CONT;//�������� ���
		 ADC1->CR2    |=  ADC_CR2_EXTSEL;
     //    ADC1->CR1|=ADC_CR1_SCAN ;
		 ADC1->CR2  |= ADC_CR2_EXTTRIG;
		// ADC1->CR1&=~ADC_CR1_DUALMOD;
		  ADC1->SMPR2&=~ ADC_SMPR2_SMP1_0; //1
		 	  ADC1->SMPR2&=~ADC_SMPR2_SMP1_1; //1
		 	   ADC1->SMPR2 &=~ ADC_SMPR2_SMP1_2; //1

		 	    ADC1->SQR3   |= ADC_SQR3_SQ1_0;   //1 IN1
		 			  ADC1->SQR3   &= ~ ADC_SQR3_SQ1_1;     //0
		 			  ADC1->SQR3   &= ~ADC_SQR3_SQ1_2;   //0
		 			  ADC1->SQR3   &=~  ADC_SQR3_SQ1_3;     //0
		 			  ADC1->SQR3   &= ~ADC_SQR3_SQ1_4;
		 			  ADC1->CR2 |=  ADC_CR2_ADON;
		 			 ADC1->CR2 |= ADC_CR2_SWSTART;
//}
//void adc2_init(void)
//{
	//RCC->CFGR &=~ RCC_CFGR_ADCPRE;
	//RCC->APB2ENR|=RCC_APB2ENR_IOPAEN;
	//		GPIOA->CRL&=~GPIO_CRL_CNF2;
		//   	GPIOA->CRL&=~ GPIO_CRL_MODE2;
		//   	RCC->APB2ENR |=  RCC_APB2ENR_ADC2EN;
		   		//	RCC->CFGR |= RCC_CFGR_ADCPRE_DIV2;
		   // ADC2->CR2 |= ADC_CR2_RSTCAL;
		   		// while (!(ADC2->CR2 & ADC_CR2_RSTCAL))
		   		// {
		   		// }

		   	//	 ADC2->CR2 |= ADC_CR2_CAL;
		   		//ADC2->CR2 |=ADC_CR2_CONT;//�������� ���
		   		//ADC2->CR2    |=  ADC_CR2_EXTSEL;
		   	//	ADC2->CR2  |= ADC_CR2_EXTTRIG;
		   		//ADC2->SMPR2&=~ ADC_SMPR2_SMP2_0; //1
		   	//	ADC2->SMPR2&=~ADC_SMPR2_SMP2_1; //1
		   	//	ADC2->SMPR2 &=~ ADC_SMPR2_SMP2_2; //1
		 //  	ADC2->SQR3   &=~ ADC_SQR3_SQ1_0;   //1 IN1
		   //	ADC2->SQR3   |=  ADC_SQR3_SQ1_1;     //0
		  // 	ADC2->SQR3   &= ~ADC_SQR3_SQ1_2;   //0
		   //	ADC2->SQR3   &=~  ADC_SQR3_SQ1_3;     //0
		  //  ADC2->SQR3   &= ~ADC_SQR3_SQ1_4;
		  //  ADC2->CR2 |=  ADC_CR2_ADON;
}
void DMA_init(void)
{
	RCC->AHBENR|=RCC_AHBENR_DMA1EN;
	DMA1_Channel1->CPAR=(uint32_t)&ADC1->DR;
    DMA1_Channel1->CMAR=(uint32_t)&TIM4->CCR1;
    DMA1_Channel1->CNDTR=1;
    DMA1_Channel1->CCR|=DMA_CCR_CIRC;
	DMA1_Channel1->CCR&=~DMA_CCR_PINC ;
	DMA1_Channel1->CCR&=~DMA_CCR_MINC;
	DMA1_Channel1->CCR|=DMA_CCR_PSIZE_0 ;
	DMA1_Channel1->CCR|=DMA_CCR_MSIZE_0;
	DMA1_Channel1->CCR&=~DMA_CCR_DIR ;
     DMA1_Channel1->CCR|=DMA_CCR_EN ;

	ADC1->CR2|=ADC_CR2_DMA;
}
void timer1_init(void)
{

	RCC-> APB2ENR 	|=RCC_APB2ENR_TIM1EN;
			 // NVIC_EnableIRQ (TIM2_IRQn);
			//TIM2->CR1&=~  TIM_CR1_CEN;
				TIM1->PSC = 2400-1; // ����������� �������� ��� ������ ����� 1000 ��� � �������
				  TIM1->ARR = 20 ;
				  TIM1->RCR=10-1;

				  TIM1->DIER |= TIM_DIER_UIE;
				  TIM1->EGR = TIM_EGR_UG ;

				  TIM1->CR1|=   TIM_CR1_CEN;
				  NVIC_EnableIRQ (TIM1_UP_IRQn);
}
void timer2_init(void)
{
	//RCC->APB2ENR|=RCC_APB2ENR_IOPAEN;

	RCC-> APB1ENR 	|=RCC_APB1ENR_TIM2EN;
   	RCC->APB2ENR|=RCC_APB2ENR_AFIOEN;
   //	GPIOA->CRH&=~GPIO_CRH_CNF15_1;
   //	GPIOA->CRH|=GPIO_CRH_CNF15_1;

   	//	GPIOA->CRH&=~GPIO_CRH_MODE15;
   	//	GPIOA->CRH|=GPIO_CRH_MODE15;
		 //  AFIO-> MAPR|=AFIO_MAPR_TIM2_REMAP ;
		 // NVIC_EnableIRQ (TIM2_IRQn);
		//TIM2->CR1&=~  TIM_CR1_CEN;
			TIM2->PSC = 0; // ����������� �������� ��� ������ ����� 1000 ��� � �������
			  TIM2->ARR = 65535 ;
			// TIM2->DIER |= TIM_DIER_UIE;
			 TIM2->EGR |= TIM_EGR_UG ;
			  TIM2->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1;
			 // TIM2->CCMR1 = TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1;
			 // TIM2->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_1;
			 // TIM2->CCMR2 = TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4M_1;
			  TIM2->CCER |=TIM_CCER_CC1E;
			// TIM2->CCER =TIM_CCER_CC2E;
			 // TIM2->CCER =TIM_CCER_CC3E;
			 // TIM2->CCER =TIM_CCER_CC4E;
			  TIM2->CCER&=~TIM_CCER_CC1P;
			  TIM2->CR1&=~TIM_CR1_DIR;
			 // NVIC_EnableIRQ (TIM2_IRQn);
			 // TIM2->CCR1=0;
			//  TIM2->CCR2=0;
			//  TIM2->CCR3=0;
			 // TIM2->CCR4=0;

			  TIM2->CR1|=   TIM_CR1_CEN;
			//  NVIC_EnableIRQ (TIM2_IRQn);
}
void timer3_init(void)
{
	RCC-> APB1ENR |=RCC_APB1ENR_TIM3EN;
	TIM3->PSC = 9; // ����������� �������� ��� ������ ����� 1000 ��� � �������
	TIM3->ARR = 7000 ;

	TIM3->EGR |= TIM_EGR_UG ;
	TIM3->CR1|=   TIM_CR1_CEN;
}
void init_pwm_timer4(void)
{

	//RCC->APB2ENR|=RCC_APB2ENR_IOPBEN ;

	 GPIOB->CRL|=GPIO_CRL_CNF6_1;
	 GPIOB->CRL&=~GPIO_CRL_CNF6_0;
   GPIOB->CRL|= GPIO_CRL_MODE6_1;
   GPIOB->CRL|= GPIO_CRL_MODE6_0;
	 //--��������� ������� ������ ���-����7------//
	 GPIOB->CRL|=GPIO_CRL_CNF7_1;
		 GPIOB->CRL&=~GPIO_CRL_CNF7_0;
	   GPIOB->CRL|= GPIO_CRL_MODE7_1;
		 GPIOB->CRL|= GPIO_CRL_MODE7_0;
		 GPIOB->CRH|=GPIO_CRH_CNF8_1;
		 GPIOB->CRH&=~GPIO_CRH_CNF8_0;
		GPIOB->CRH|= GPIO_CRH_MODE8_1;
		GPIOB->CRH|= GPIO_CRH_MODE8_0;

		  //--��������� ������� ������ ���-����9------//
		   GPIOB->CRH|=GPIO_CRH_CNF9_1;
				 GPIOB->CRH&=~GPIO_CRH_CNF9_0;
				GPIOB->CRH|= GPIO_CRH_MODE9_1;
				GPIOB->CRH|= GPIO_CRH_MODE9_0;
	// RCC->APB2ENR|=RCC_APB2ENR_AFIOEN;
	AFIO->MAPR&=~AFIO_MAPR_TIM4_REMAP;
	RCC->APB1ENR|= RCC_APB1ENR_TIM4EN ;
	TIM4->PSC= 0;
	TIM4->ARR= 4095;
	//TIM4->CCMR1&=~TIM_CCMR1_CC1S;//��������� ������ 1 �� �����.
	TIM4->CCMR1&=~TIM_CCMR1_CC2S;//��������� ������ 2 �� �����.
	TIM4->CCMR2&=~TIM_CCMR2_CC3S;
	TIM4->CCMR2&=~TIM_CCMR2_CC4S;
	//TIM4->CR1&=~TIM_CR1_DIR;
	TIM4->CCMR1|= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1;//|TIM_CCMR1_OC1M_0;//;//
	TIM4->CCMR1|= TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1;//|TIM_CCMR1_OC2M_0;//
	TIM4->CCMR2|= TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_1;//|TIM_CCMR1_OC2M_0;//
	TIM4->CCMR2|= TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4M_1;


	TIM4->CCMR1|=TIM_CCMR1_OC1PE;
	TIM4->CCMR1|=TIM_CCMR1_OC2PE;
	TIM4->CCMR2|=TIM_CCMR2_OC3PE;
	TIM4->CCMR2|=TIM_CCMR2_OC4PE;




	 TIM4->CCER |=TIM_CCER_CC1E;
	 TIM4->CCER |=TIM_CCER_CC2E;
	 TIM4->CCER |=TIM_CCER_CC3E;
	 TIM4->CCER |=TIM_CCER_CC4E;
	// TIM4->CCER &=~TIM_CCER_CC1P;
	 TIM4->CCER &=~TIM_CCER_CC2P;
	 TIM4->CCER &=~TIM_CCER_CC3P;
	 TIM4->CCER &=~TIM_CCER_CC4P;
	// TIM4->CR1|=TIM_CR1_ARPE;
    //TIM4->EGR|= TIM_EGR_UG;
     // TIM4->CCR1=30000;
    TIM4->CR1|=  TIM_CR1_CEN;
}

void IWDT_init(void)
{
	          RCC->CSR|= RCC_CSR_LSION;


		   IWDG->KR = 0x5555; // Access to registers
		   IWDG->PR&= ~(IWDG_PR_PR_0 | IWDG_PR_PR_1 | IWDG_PR_PR_2); // 4096
		   IWDG->RLR =  2000;//0x7FF;
		   while (!((IWDG->SR & IWDG_SR_PVU) && (IWDG->SR & IWDG_SR_RVU))){} // wait while bist of PVU and RVU will be set.
		   IWDG->KR = 0xCCCC; // Start count down;
}

int main(void)
{
	//init_systimer();
	 //RCC_DeInit();
	 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);
	  //Delay after an RCC peripheral clock enabling
	  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);
	  //NOJTAG: JTAG-DP Disabled and SW-DP Enabled
	//SetSysClockTo72();
	RCC_init();
	init_systimer();
	APB_init();

		GPIOC_init();

	IWDT_init();
	timer1_init();
	//timer2_init();
	//timer3_init();
	usart1_init();
	// USART1_Init();
	//init_pwm_timer4();

	//adc1_init();
	//DMA_init();
	//adc2_init();
	// ADC1->CR1|= ADC_CR1_EOCIE;
	// ADC2->CR1|= ADC_CR1_EOCIE;
	// ADC1->CR2 |=  ADC_CR2_ADON;
	 //ADC2->CR2 |=  ADC_CR2_ADON;

    // NVIC_EnableIRQ ( ADC1_2_IRQn);


	//ADC1->CR2 |= ADC_CR2_SWSTART;
//	ADC2->CR2 |= ADC_CR2_SWSTART;
	// ADC1->CR2 |=  ADC_CR2_EXTSEL_2;
	//TIM2->CCR1=1000;
	while(1)
	{
	   // TIM4->CCR1=65535;
       // TIM4->CCR1=bufer;
		//tx_str1("mama");
		tx_uart('m');
		tx_uart('a');
		//tx_uart('m');
	   // tx_uart('a');
		delay_ms(500);
		//ADC1->CR2 |= ADC_CR2_SWSTART;
		//ADC2->CR2 |= ADC_CR2_SWSTART;
		  // ADC1->CR2    |=  ADC_CR2_EXTSEL_2;
		 // while (!(ADC1->SR & ADC_SR_EOC));
		//  while (!(ADC2->SR & ADC_SR_EOC));
		 //  ADC1->SR &=~ ADC_SR_EOC;
		//   ADC2->SR &=~ ADC_SR_EOC;
		 //  adc_data1 = ADC1->DR;
		 //  TIM4->CCR1=adc_data1*16;
		//   ADC1->DR=0;
	//	 ADC2->CR2    |=  ADC_CR2_EXTSEL_2;
		 // while (!(ADC2->SR & ADC_SR_EOC)); //���� ���� ������ �������������� ����������
		//ADC1->SR &=~ ADC_SR_EOC;
		//ADC2->SR &=~ ADC_SR_EOC;
		// adc_data1 = ADC1->DR;
		//   adc_data2 = ADC2->DR;
		 //  TIM4->CCR1=adc_data1*16;
		// TIM4->CCR2=adc_data2*16;
	//	TIM4->CCR2=4095;
	//	 TIM4->CCR3=4095;
		// TIM4->CCR4=4095;
		// TIM4->CCR2=65535;

	}
}
void SysTick_Handler(void)
{
  if(SysTick_CNT > 0)  SysTick_CNT--;
}