.include "m2561def.inc"
.include "macros_v1.72.asm"
.include "Var.asm"



.CSEG

; ---------------  ------

 	ldi r16,high(RAMEND) ;      
	out SPH,r16 ;                
 	ldi r16,low(RAMEND)  
 	out SPL,r16 



;------  UART --------

uart_init:	
			ldi 	R16, 0x00     ; Baudrate = 115200
			sts 	UBRR0H,R16    ;
			ldi 	R16, 0x19     ;    08   ----------
			sts 	UBRR0L,R16    ;


			ldi 	R16, 0x00 	  ; U2X=0  
			sts 	UCSR0A,R16    ;  

			ldi 	R16, 0x18	  ;    
			sts 	UCSR0B,R16    ;     
								  ;,   
								  ;  UDR
								  ; 8 -  


			ldi 	R16, 0x06	  ;  
			sts 	UCSR0C,R16    ;  
								  ; 1  
								  ; 8- 
								  ; -TD, -RD 


;------   --------

		ldi r17, 0x00
 		out PINE, r17  ;  Pull-up  

 		ldi r17, 0x08
 		out DDRE, r17  ;       SHDN  ADM222

		ldi r17, 0x00
 		out PINB, r17  ;  Pull-up  

 		ldi r17, 0x60
 		out DDRB, r17  ;      

 		ldi r17, 0x00   ;    
 		out DDRA, r17
 		out DDRC, r17
 		out DDRD, r17
 		out DDRF, r17
 		out DDRG, r17
 
 		ldi r18,0x60
		out PORTB, r18
		



;-------------   ------------

rcall SPI_MasterInit
rcall SPI_MasterTransmit
rcall SPI_MasterReceive
rcall uart_snt
  

finito:
nop
rjmp finito

;-----------------------------------------------



;***********************************************************************
;---------------    Master  SPI --------------------
;PB0 - SS
;PB1 - SCLK
;PB2 - MOSI
;PB3 - MISO
;
			SPI_MasterInit:

				;  MOSI  SCK  ,    
				ldi 	r19,(0<<PB3)|(1<<PB2)|(1<<PB1)|(0<<PB0)
				out		DDRB,r18
				rcall Waiting2
				;  SPI   ,  fclk/4,  0
				ldi 	r18,(1<<SPE)|(1<<MSTR)|(0<<SPR1)|(0<<SPR0)|(0<<CPOL)|(0<<CPHA);0x5f;
				sts 	SPCR,r18
				rcall Waiting2
            ret



;---------------   SPI --------------------

			SPI_MasterTransmit:
				ldi r16,0xD7		;  OPCODE   -
				out SPDR,r16
		Wait_Transmit:				; Wait for transmission complete
				lds r18, SPSR 
				sbrs r18,SPIF
				rjmp Wait_Transmit
             ret

;---------------   SPI --------------------

		SPI_MasterReceive:
				lds r18, SPSR 			; Wait for reception complete
			    sbrs r18,SPIF
	              	rjmp SPI_MasterReceive
				; Read received data and return
			in r21,SPDR
			ret
		
;********************************************************************************




;**************************************************
;*      ;;+ ;;*      *
;**************************************************

Waiting2:

		 ldi r19, 0x7F
		  fin22:
		   dec r19
		   cpi r19, 0x00
		  brne fin22
		     nop
    ret



;**************************************************
;*      ;;+   UART - ;;*      *
;**************************************************
;-----         -------
			
uart_snt:
			lds r23, UCSR0A			
			SBRS 	r23,UDRE0	;     ,
								;   1 -    
			RJMP	uart_snt 	;   -  UDRE
			sts	    UDR0, r21	;  ,   
			break
		RET					; 



		
