System Settings

 
Environment Settings
Environment Variable xst ngdbuild
PATHEXT .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC		 .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC
Path C:\Xilinx\12.2\ISE_DS\ISE\\lib\nt;
C:\Xilinx\12.2\ISE_DS\ISE\\bin\nt;
C:\Xilinx\12.2\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.2\ISE_DS\ISE\bin\nt;
C:\Xilinx\12.2\ISE_DS\ISE\lib\nt;
C:\Xilinx\12.2\ISE_DS\EDK\bin\nt;
C:\Xilinx\12.2\ISE_DS\EDK\lib\nt;
C:\Xilinx\12.2\ISE_DS\common\bin\nt;
C:\Xilinx\12.2\ISE_DS\common\lib\nt;
C:\Program Files\Common Files\Microsoft Shared\Windows Live;
C:\Program Files\AMD APP\bin\x86;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files\Windows Live\Shared		 C:\Xilinx\12.2\ISE_DS\ISE\\lib\nt;
C:\Xilinx\12.2\ISE_DS\ISE\\bin\nt;
C:\Xilinx\12.2\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.2\ISE_DS\ISE\bin\nt;
C:\Xilinx\12.2\ISE_DS\ISE\lib\nt;
C:\Xilinx\12.2\ISE_DS\EDK\bin\nt;
C:\Xilinx\12.2\ISE_DS\EDK\lib\nt;
C:\Xilinx\12.2\ISE_DS\common\bin\nt;
C:\Xilinx\12.2\ISE_DS\common\lib\nt;
C:\Program Files\Common Files\Microsoft Shared\Windows Live;
C:\Program Files\AMD APP\bin\x86;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files\Windows Live\Shared
XILINX C:\Xilinx\12.2\ISE_DS\ISE\ C:\Xilinx\12.2\ISE_DS\ISE\
XILINX_DSP C:\Xilinx\12.2\ISE_DS\ISE C:\Xilinx\12.2\ISE_DS\ISE
XILINX_EDK C:\Xilinx\12.2\ISE_DS\EDK C:\Xilinx\12.2\ISE_DS\EDK
XILINX_PLANAHEAD C:\Xilinx\12.2\ISE_DS\PlanAhead C:\Xilinx\12.2\ISE_DS\PlanAhead
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   controller.prj  
-ifmt   mixed MIXED
-ofn   controller  
-ofmt   NGC NGC
-p   xc9500xl  
-top   controller  
-opt_mode Optimization Goal Speed Speed
-opt_level Optimization Effort 1 1
-iuc Use synthesis Constraints File NO NO
-keep_hierarchy Keep Hierarchy Yes YES
-netlist_hierarchy Netlist Hierarchy As_Optimized As_Optimized
-rtlview Generate RTL Schematic Yes NO
-bus_delimiter Bus Delimiter <> <>
-verilog2001 Verilog 2001 YES YES
-fsm_extract   YES YES
-fsm_encoding   Auto AUTO
-safe_implementation   No NO
-resource_sharing   YES YES
-iobuf   YES YES
-equivalent_register_removal   YES YES
 
Translation Property Settings
Switch Name Property Name Value Default Value
-intstyle   ise None
-dd   _ngo None
-p   xc9572xl-VQ44-10 None
 
Operating System Information
Operating System Information xst ngdbuild
CPU Architecture/Speed Intel(R) Core(TM)2 Duo CPU E7300 @ 2.66GHz/2666 MHz Intel(R) Core(TM)2 Duo CPU E7300 @ 2.66GHz/2666 MHz
Host nick17_My nick17_My
OS Name Microsoft Microsoft
OS Release Service Pack 1 (build 7601) Service Pack 1 (build 7601)