cpldfit: version M.63c Xilinx Inc.
Fitter Report
Design Name: controller Date: 8-14-2011, 9:25PM
Device Used: XC9572XL-10-VQ44
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
61 /72 ( 85%) 242 /360 ( 67%) 111/216 ( 51%) 55 /72 ( 76%) 18 /34 ( 53%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 32/54 65/90 7/ 9
FB2 9/18 32/54 82/90 5/ 9
FB3 17/18 28/54 61/90 3/ 9
FB4 17/18 19/54 34/90 3/ 7
----- ----- ----- -----
61/72 111/216 242/360 18/34
* - Resource is exhausted
** Global Control Resources **
Signal 'CLK' mapped onto global clock net GCK1.
Signal 'SER_CLK' mapped onto global clock net GCK2.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 11 11 | I/O : 16 28
Output : 4 4 | GCK/IO : 2 3
Bidirectional : 1 1 | GTS/IO : 0 2
GCK : 2 2 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 18 18
** Power Data **
There are 61 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
use the default filename of 'controller.ise'.
************************* Summary of Mapped Logic ************************
** 5 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
FIFO_CLK 5 7 FB1_2 39 I/O O STD FAST
ADC_CLK 5 7 FB1_6 41 I/O O STD FAST
SER_DATA 3 3 FB1_15 2 I/O I/O STD FAST RESET
UC_CLK 1 1 FB2_2 29 I/O O STD FAST RESET
TST_LED 1 7 FB2_8 32 I/O O STD FAST RESET
** 56 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
CNT_1<6> 1 6 FB1_1 STD RESET
CNT_1<5> 1 5 FB1_3 STD RESET
CNT_1<4> 1 4 FB1_4 STD RESET
REG_DIV<2> 2 3 FB1_5 STD RESET
REG_DIV<1> 2 3 FB1_7 STD RESET
REG_KEY<0> 3 4 FB1_8 STD RESET
REG_KEY<7> 4 5 FB1_9 STD RESET
REG_KEY<6> 4 5 FB1_10 STD RESET
REG_KEY<5> 4 5 FB1_11 STD RESET
REG_KEY<4> 4 5 FB1_12 STD RESET
REG_KEY<3> 4 5 FB1_13 STD RESET
REG_KEY<2> 4 5 FB1_14 STD RESET
REG_KEY<1> 4 5 FB1_16 STD RESET
OUT_CNT_2/OUT_CNT_2_CLKF 5 6 FB1_17 STD
OUT_TMP 9 11 FB1_18 STD RESET
CNT_1<2> 1 2 FB2_3 STD RESET
CNT_1<0> 0 0 FB2_4 STD RESET
CNT_2<0> 17 18 FB2_5 STD RESET
CNT_1<3> 1 3 FB2_7 STD RESET
$OpTx$BUF_OUT_CNT_2_INV$424 17 17 FB2_10 STD
OUT_CNT_2 18 18 FB2_15 STD RESET
CNT_2<13> 26 25 FB2_18 STD RESET
$OpTx$INV$34 16 16 FB3_1 STD
CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2 1 14 FB3_2 STD
REG_CMP<10> 2 3 FB3_3 STD RESET
CNT_2<9> 3 12 FB3_4 STD RESET
CNT_2<8> 3 11 FB3_5 STD RESET
CNT_2<7> 3 10 FB3_6 STD RESET
CNT_2<6> 3 9 FB3_7 STD RESET
CNT_2<5> 3 8 FB3_8 STD RESET
CNT_2<4> 3 7 FB3_9 STD RESET
CNT_2<3> 3 6 FB3_10 STD RESET
CNT_2<2> 3 5 FB3_11 STD RESET
CNT_2<1> 3 4 FB3_12 STD RESET
CNT_2<15> 3 18 FB3_13 STD RESET
CNT_2<14> 3 17 FB3_14 STD RESET
CNT_2<12> 3 15 FB3_15 STD RESET
CNT_2<11> 3 14 FB3_16 STD RESET
CNT_2<10> 3 13 FB3_17 STD RESET
REG_DIV<3> 2 3 FB4_2 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
REG_DIV<0> 2 3 FB4_3 STD RESET
REG_CMP<9> 2 3 FB4_4 STD RESET
REG_CMP<8> 2 3 FB4_5 STD RESET
REG_CMP<7> 2 3 FB4_6 STD RESET
REG_CMP<6> 2 3 FB4_7 STD RESET
REG_CMP<5> 2 3 FB4_8 STD RESET
REG_CMP<4> 2 3 FB4_9 STD RESET
REG_CMP<3> 2 3 FB4_10 STD RESET
REG_CMP<2> 2 3 FB4_11 STD RESET
REG_CMP<1> 2 3 FB4_12 STD RESET
REG_CMP<15> 2 3 FB4_13 STD RESET
REG_CMP<14> 2 3 FB4_14 STD RESET
REG_CMP<13> 2 3 FB4_15 STD RESET
REG_CMP<12> 2 3 FB4_16 STD RESET
REG_CMP<11> 2 3 FB4_17 STD RESET
REG_CMP<0> 2 3 FB4_18 STD RESET
** 13 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
DIN_SV5<0> FB1_5 40 I/O I
CLK FB1_9 43~ GCK/I/O GCK/I
SER_CLK FB1_11 44~ GCK/I/O GCK
DIN_SV5<6> FB1_17 3 I/O I
DIN_SV5<4> FB2_5 30 I/O I
SER_GATE FB2_6 31 I/O I
SER_RDWR FB2_17 38 I/O I
SER_EN FB3_5 6 I/O I
DIN_SV5<5> FB3_11 12 I/O I
DIN_SV5<1> FB3_14 13 I/O I
DIN_SV5<3> FB4_11 22 I/O I
DIN_SV5<2> FB4_14 23 I/O I
DIN_SV5<7> FB4_17 28 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 32/22
Number of signals used by logic mapping into function block: 32
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
CNT_1<6> 1 0 /\4 0 FB1_1 (b) (b)
FIFO_CLK 5 0 0 0 FB1_2 39 I/O O
CNT_1<5> 1 0 0 4 FB1_3 (b) (b)
CNT_1<4> 1 0 0 4 FB1_4 (b) (b)
REG_DIV<2> 2 0 0 3 FB1_5 40 I/O I
ADC_CLK 5 0 0 0 FB1_6 41 I/O O
REG_DIV<1> 2 0 0 3 FB1_7 (b) (b)
REG_KEY<0> 3 0 0 2 FB1_8 42 I/O (b)
REG_KEY<7> 4 0 0 1 FB1_9 43 GCK/I/O GCK/I
REG_KEY<6> 4 0 0 1 FB1_10 (b) (b)
REG_KEY<5> 4 0 0 1 FB1_11 44 GCK/I/O GCK
REG_KEY<4> 4 0 0 1 FB1_12 (b) (b)
REG_KEY<3> 4 0 0 1 FB1_13 (b) (b)
REG_KEY<2> 4 0 0 1 FB1_14 1 GCK/I/O (b)
SER_DATA 3 0 0 2 FB1_15 2 I/O I/O
REG_KEY<1> 4 0 0 1 FB1_16 (b) (b)
OUT_CNT_2/OUT_CNT_2_CLKF
5 0 0 0 FB1_17 3 I/O I
OUT_TMP 9 4<- 0 0 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: CLK 12: DIN_SV5<5> 23: REG_KEY<2>
2: CNT_1<0> 13: DIN_SV5<6> 24: REG_KEY<3>
3: CNT_1<2> 14: DIN_SV5<7> 25: REG_KEY<4>
4: CNT_1<3> 15: OUT_CNT_2 26: REG_KEY<5>
5: CNT_1<4> 16: OUT_TMP 27: REG_KEY<6>
6: CNT_1<5> 17: REG_DIV<0> 28: REG_KEY<7>
7: DIN_SV5<0> 18: REG_DIV<1> 29: SER_EN
8: DIN_SV5<1> 19: REG_DIV<2> 30: SER_GATE
9: DIN_SV5<2> 20: REG_DIV<3> 31: SER_RDWR
10: DIN_SV5<3> 21: REG_KEY<0> 32: UC_CLK
11: DIN_SV5<4> 22: REG_KEY<1>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
CNT_1<6> .XXXXX.........................X........ 6
FIFO_CLK X.............X.XXXX.........X.......... 7
CNT_1<5> .XXXX..........................X........ 5
CNT_1<4> .XXX...........................X........ 4
REG_DIV<2> .................X..........X.X......... 3
ADC_CLK X.............X.XXXX.........X.......... 7
REG_DIV<1> ................X...........X.X......... 3
REG_KEY<0> ......X.............X.......X.X......... 4
REG_KEY<7> .............X............XXX.X......... 5
REG_KEY<6> ............X............XX.X.X......... 5
REG_KEY<5> ...........X............XX..X.X......... 5
REG_KEY<4> ..........X............XX...X.X......... 5
REG_KEY<3> .........X............XX....X.X......... 5
REG_KEY<2> ........X............XX.....X.X......... 5
SER_DATA ...........................XX.X......... 3
REG_KEY<1> .......X............XX......X.X......... 5
OUT_CNT_2/OUT_CNT_2_CLKF
X..............XXXXX.................... 6
OUT_TMP .XXXXX.........XXXXX...........X........ 11
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 32/22
Number of signals used by logic mapping into function block: 32
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 /\5 0 FB2_1 (b) (b)
UC_CLK 1 1<- /\5 0 FB2_2 29 I/O O
CNT_1<2> 1 0 /\1 3 FB2_3 (b) (b)
CNT_1<0> 0 0 \/4 1 FB2_4 (b) (b)
CNT_2<0> 17 12<- 0 0 FB2_5 30 I/O I
(unused) 0 0 /\5 0 FB2_6 31 I/O I
CNT_1<3> 1 0 /\3 1 FB2_7 (b) (b)
TST_LED 1 0 \/2 2 FB2_8 32 I/O O
(unused) 0 0 \/5 0 FB2_9 33 GSR/I/O (b)
$OpTx$BUF_OUT_CNT_2_INV$424
17 12<- 0 0 FB2_10 (b) (b)
(unused) 0 0 /\5 0 FB2_11 34 GTS/I/O (b)
(unused) 0 0 \/4 1 FB2_12 (b) (b)
(unused) 0 0 \/5 0 FB2_13 (b) (b)
(unused) 0 0 \/5 0 FB2_14 36 GTS/I/O (b)
OUT_CNT_2 18 14<- \/1 0 FB2_15 37 I/O (b)
(unused) 0 0 \/5 0 FB2_16 (b) (b)
(unused) 0 0 \/5 0 FB2_17 38 I/O I
CNT_2<13> 26 21<- 0 0 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$INV$34 12: CNT_2<13> 23: OUT_CNT_2/OUT_CNT_2_CLKF
2: CNT_1<0> 13: CNT_2<1> 24: REG_CMP<0>
3: CNT_1<2> 14: CNT_2<2> 25: REG_CMP<13>
4: CNT_1<3> 15: CNT_2<3> 26: REG_CMP<1>
5: CNT_1<4> 16: CNT_2<4> 27: REG_CMP<2>
6: CNT_1<5> 17: CNT_2<5> 28: REG_CMP<3>
7: CNT_1<6> 18: CNT_2<6> 29: REG_CMP<4>
8: CNT_2<0> 19: CNT_2<7> 30: REG_CMP<6>
9: CNT_2<10> 20: CNT_2<8> 31: REG_CMP<7>
10: CNT_2<11> 21: CNT_2<9> 32: UC_CLK
11: CNT_2<12> 22: CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
UC_CLK .X...................................... 1
CNT_1<2> .X.............................X........ 2
CNT_1<0> ........................................ 0
CNT_2<0> X......X...XXXXX.XX...XXXXXXXXX......... 18
CNT_1<3> .XX............................X........ 3
TST_LED .XXXXXX........................X........ 7
$OpTx$BUF_OUT_CNT_2_INV$424
X......X...XXXXX.XX....XXXXXXXX......... 17
OUT_CNT_2 X......X...XXXXX.XX...XXXXXXXXX......... 18
CNT_2<13> X......XXXXXXXXXXXXXXXXXXXXXXXX......... 25
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 28/26
Number of signals used by logic mapping into function block: 28
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
$OpTx$INV$34 16 11<- 0 0 FB3_1 (b) (b)
CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2
1 0 /\4 0 FB3_2 5 I/O (b)
REG_CMP<10> 2 0 0 3 FB3_3 (b) (b)
CNT_2<9> 3 0 0 2 FB3_4 (b) (b)
CNT_2<8> 3 0 0 2 FB3_5 6 I/O I
CNT_2<7> 3 0 0 2 FB3_6 (b) (b)
CNT_2<6> 3 0 0 2 FB3_7 (b) (b)
CNT_2<5> 3 0 0 2 FB3_8 7 I/O (b)
CNT_2<4> 3 0 0 2 FB3_9 8 I/O (b)
CNT_2<3> 3 0 0 2 FB3_10 (b) (b)
CNT_2<2> 3 0 0 2 FB3_11 12 I/O I
CNT_2<1> 3 0 0 2 FB3_12 (b) (b)
CNT_2<15> 3 0 0 2 FB3_13 (b) (b)
CNT_2<14> 3 0 0 2 FB3_14 13 I/O I
CNT_2<12> 3 0 0 2 FB3_15 14 I/O (b)
CNT_2<11> 3 0 0 2 FB3_16 18 I/O (b)
CNT_2<10> 3 0 \/2 0 FB3_17 16 I/O (b)
(unused) 0 0 \/5 0 FB3_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$BUF_OUT_CNT_2_INV$424 11: CNT_2<3> 20: REG_CMP<11>
2: CNT_2<0> 12: CNT_2<4> 21: REG_CMP<12>
3: CNT_2<10> 13: CNT_2<5> 22: REG_CMP<14>
4: CNT_2<11> 14: CNT_2<6> 23: REG_CMP<15>
5: CNT_2<12> 15: CNT_2<7> 24: REG_CMP<5>
6: CNT_2<13> 16: CNT_2<8> 25: REG_CMP<8>
7: CNT_2<14> 17: CNT_2<9> 26: REG_CMP<9>
8: CNT_2<15> 18: OUT_CNT_2/OUT_CNT_2_CLKF 27: SER_EN
9: CNT_2<1> 19: REG_CMP<10> 28: SER_RDWR
10: CNT_2<2>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
$OpTx$INV$34 ..XXX.XX....X..XX.XXXXXXXX.............. 16
CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2
.XXXXX..XXXXXXXXX....................... 14
REG_CMP<10> .........................XXX............ 3
CNT_2<9> XX......XXXXXXXXXX...................... 12
CNT_2<8> XX......XXXXXXXX.X...................... 11
CNT_2<7> XX......XXXXXXX..X...................... 10
CNT_2<6> XX......XXXXXX...X...................... 9
CNT_2<5> XX......XXXXX....X...................... 8
CNT_2<4> XX......XXXX.....X...................... 7
CNT_2<3> XX......XXX......X...................... 6
CNT_2<2> XX......XX.......X...................... 5
CNT_2<1> XX......X........X...................... 4
CNT_2<15> XXXXXXXXXXXXXXXXXX...................... 18
CNT_2<14> XXXXXXX.XXXXXXXXXX...................... 17
CNT_2<12> XXXXX...XXXXXXXXXX...................... 15
CNT_2<11> XXXX....XXXXXXXXXX...................... 14
CNT_2<10> XXX.....XXXXXXXXXX...................... 13
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 19/35
Number of signals used by logic mapping into function block: 19
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB4_1 (b)
REG_DIV<3> 2 0 0 3 FB4_2 19 I/O (b)
REG_DIV<0> 2 0 0 3 FB4_3 (b) (b)
REG_CMP<9> 2 0 0 3 FB4_4 (b) (b)
REG_CMP<8> 2 0 0 3 FB4_5 20 I/O (b)
REG_CMP<7> 2 0 0 3 FB4_6 (b) (b)
REG_CMP<6> 2 0 0 3 FB4_7 (b) (b)
REG_CMP<5> 2 0 0 3 FB4_8 21 I/O (b)
REG_CMP<4> 2 0 0 3 FB4_9 (b) (b)
REG_CMP<3> 2 0 0 3 FB4_10 (b) (b)
REG_CMP<2> 2 0 0 3 FB4_11 22 I/O I
REG_CMP<1> 2 0 0 3 FB4_12 (b) (b)
REG_CMP<15> 2 0 0 3 FB4_13 (b) (b)
REG_CMP<14> 2 0 0 3 FB4_14 23 I/O I
REG_CMP<13> 2 0 0 3 FB4_15 27 I/O (b)
REG_CMP<12> 2 0 0 3 FB4_16 (b) (b)
REG_CMP<11> 2 0 0 3 FB4_17 28 I/O I
REG_CMP<0> 2 0 0 3 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: SER_DATA.PIN 8: REG_CMP<15> 14: REG_CMP<6>
2: REG_CMP<0> 9: REG_CMP<1> 15: REG_CMP<7>
3: REG_CMP<10> 10: REG_CMP<2> 16: REG_CMP<8>
4: REG_CMP<11> 11: REG_CMP<3> 17: REG_DIV<2>
5: REG_CMP<12> 12: REG_CMP<4> 18: SER_EN
6: REG_CMP<13> 13: REG_CMP<5> 19: SER_RDWR
7: REG_CMP<14>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
REG_DIV<3> ................XXX..................... 3
REG_DIV<0> .......X.........XX..................... 3
REG_CMP<9> ...............X.XX..................... 3
REG_CMP<8> ..............X..XX..................... 3
REG_CMP<7> .............X...XX..................... 3
REG_CMP<6> ............X....XX..................... 3
REG_CMP<5> ...........X.....XX..................... 3
REG_CMP<4> ..........X......XX..................... 3
REG_CMP<3> .........X.......XX..................... 3
REG_CMP<2> ........X........XX..................... 3
REG_CMP<1> .X...............XX..................... 3
REG_CMP<15> ......X..........XX..................... 3
REG_CMP<14> .....X...........XX..................... 3
REG_CMP<13> ....X............XX..................... 3
REG_CMP<12> ...X.............XX..................... 3
REG_CMP<11> ..X..............XX..................... 3
REG_CMP<0> X................XX..................... 3
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
$OpTx$BUF_OUT_CNT_2_INV$424 <= (($OpTx$INV$34)
OR (CNT_1(7).EXP)
OR (REG_CMP(13) AND NOT CNT_2(13))
OR (NOT REG_CMP(13) AND CNT_2(13))
OR (REG_CMP(3) AND NOT CNT_2(3))
OR (NOT REG_CMP(3) AND CNT_2(3))
OR (NOT REG_CMP(4) AND CNT_2(4))
OR (REG_CMP(2) AND NOT CNT_2(2))
OR (NOT REG_CMP(2) AND CNT_2(2))
OR (REG_CMP(4) AND NOT CNT_2(4))
OR (REG_CMP(6) AND NOT CNT_2(6))
OR (NOT REG_CMP(6) AND CNT_2(6))
OR (REG_CMP(1) AND NOT CNT_2(1))
OR (NOT REG_CMP(1) AND CNT_2(1))
OR (REG_CMP(7) AND NOT CNT_2(7))
OR (NOT REG_CMP(7) AND CNT_2(7)));
$OpTx$INV$34 <= ((REG_CMP(12) AND NOT CNT_2(12))
OR (NOT REG_CMP(12) AND CNT_2(12))
OR (REG_CMP(15) AND NOT CNT_2(15))
OR (NOT REG_CMP(15) AND CNT_2(15))
OR (CNT_2(10).EXP)
OR (REG_CMP(14) AND NOT CNT_2(14))
OR (NOT REG_CMP(14) AND CNT_2(14))
OR (REG_CMP(5) AND NOT CNT_2(5))
OR (REG_CMP(8) AND NOT CNT_2(8))
OR (NOT REG_CMP(8) AND CNT_2(8))
OR (REG_CMP(10) AND NOT CNT_2(10))
OR (NOT REG_CMP(10) AND CNT_2(10))
OR (REG_CMP(11) AND NOT CNT_2(11))
OR (NOT REG_CMP(11) AND CNT_2(11))
OR (NOT REG_CMP(5) AND CNT_2(5)));
ADC_CLK <= NOT (((NOT REG_DIV(2) AND SER_GATE AND OUT_CNT_2)
OR (NOT REG_DIV(1) AND SER_GATE AND OUT_CNT_2)
OR (NOT REG_DIV(0) AND SER_GATE AND OUT_CNT_2)
OR (REG_DIV(3) AND SER_GATE AND OUT_CNT_2)
OR (REG_DIV(2) AND REG_DIV(1) AND REG_DIV(0) AND
NOT REG_DIV(3) AND SER_GATE AND CLK)));
FTCPE_CNT_10: FTCPE port map (CNT_1(0),'1',CLK,'0','0');
FTCPE_CNT_12: FTCPE port map (CNT_1(2),CNT_1_T(2),CLK,'0','0');
CNT_1_T(2) <= (UC_CLK AND CNT_1(0));
FTCPE_CNT_13: FTCPE port map (CNT_1(3),CNT_1_T(3),CLK,'0','0');
CNT_1_T(3) <= (UC_CLK AND CNT_1(0) AND CNT_1(2));
FTCPE_CNT_14: FTCPE port map (CNT_1(4),CNT_1_T(4),CLK,'0','0');
CNT_1_T(4) <= (UC_CLK AND CNT_1(0) AND CNT_1(2) AND CNT_1(3));
FTCPE_CNT_15: FTCPE port map (CNT_1(5),CNT_1_T(5),CLK,'0','0');
CNT_1_T(5) <= (UC_CLK AND CNT_1(0) AND CNT_1(2) AND CNT_1(3) AND
CNT_1(4));
FTCPE_CNT_16: FTCPE port map (CNT_1(6),CNT_1_T(6),CLK,'0','0');
CNT_1_T(6) <= (UC_CLK AND CNT_1(0) AND CNT_1(2) AND CNT_1(3) AND
CNT_1(4) AND CNT_1(5));
FDCPE_CNT_20: FDCPE port map (CNT_2(0),CNT_2_D(0),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
CNT_2_D(0) <= ((REG_CMP(13) AND NOT CNT_2(0) AND NOT CNT_2(13))
OR (NOT REG_CMP(13) AND NOT CNT_2(0) AND CNT_2(13))
OR (REG_CMP(1) AND NOT CNT_2(0) AND NOT CNT_2(1))
OR (NOT REG_CMP(1) AND NOT CNT_2(0) AND CNT_2(1))
OR (CNT_1(3).EXP)
OR (REG_CMP(3) AND NOT CNT_2(0) AND NOT CNT_2(3))
OR (NOT REG_CMP(3) AND NOT CNT_2(0) AND CNT_2(3))
OR (REG_CMP(4) AND NOT CNT_2(0) AND NOT CNT_2(4))
OR (NOT REG_CMP(4) AND NOT CNT_2(0) AND CNT_2(4))
OR (NOT REG_CMP(6) AND NOT CNT_2(0) AND CNT_2(6))
OR (REG_CMP(0) AND NOT CNT_2(0))
OR (NOT CNT_2(0) AND $OpTx$INV$34)
OR (REG_CMP(7) AND NOT CNT_2(0) AND NOT CNT_2(7))
OR (NOT REG_CMP(7) AND NOT CNT_2(0) AND CNT_2(7)));
FDCPE_CNT_21: FDCPE port map (CNT_2(1),CNT_2_D(1),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
CNT_2_D(1) <= ((CNT_2(0) AND NOT CNT_2(1) AND
$OpTx$BUF_OUT_CNT_2_INV$424)
OR (NOT CNT_2(0) AND CNT_2(1) AND
$OpTx$BUF_OUT_CNT_2_INV$424));
FTCPE_CNT_22: FTCPE port map (CNT_2(2),CNT_2_T(2),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
CNT_2_T(2) <= ((CNT_2(2) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
OR (CNT_2(0) AND CNT_2(1) AND
$OpTx$BUF_OUT_CNT_2_INV$424));
FTCPE_CNT_23: FTCPE port map (CNT_2(3),CNT_2_T(3),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
CNT_2_T(3) <= ((CNT_2(3) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
OR (CNT_2(0) AND CNT_2(1) AND CNT_2(2) AND
$OpTx$BUF_OUT_CNT_2_INV$424));
FTCPE_CNT_24: FTCPE port map (CNT_2(4),CNT_2_T(4),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
CNT_2_T(4) <= ((CNT_2(4) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
OR (CNT_2(0) AND CNT_2(1) AND CNT_2(2) AND CNT_2(3) AND
$OpTx$BUF_OUT_CNT_2_INV$424));
FTCPE_CNT_25: FTCPE port map (CNT_2(5),CNT_2_T(5),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
CNT_2_T(5) <= ((CNT_2(5) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
OR (CNT_2(0) AND CNT_2(1) AND CNT_2(2) AND CNT_2(3) AND
CNT_2(4) AND $OpTx$BUF_OUT_CNT_2_INV$424));
FTCPE_CNT_26: FTCPE port map (CNT_2(6),CNT_2_T(6),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
CNT_2_T(6) <= ((CNT_2(6) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
OR (CNT_2(0) AND CNT_2(1) AND CNT_2(2) AND CNT_2(3) AND
CNT_2(4) AND CNT_2(5) AND $OpTx$BUF_OUT_CNT_2_INV$424));
FTCPE_CNT_27: FTCPE port map (CNT_2(7),CNT_2_T(7),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
CNT_2_T(7) <= ((CNT_2(7) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
OR (CNT_2(0) AND CNT_2(1) AND CNT_2(2) AND CNT_2(3) AND
CNT_2(4) AND CNT_2(5) AND CNT_2(6) AND
$OpTx$BUF_OUT_CNT_2_INV$424));
FTCPE_CNT_28: FTCPE port map (CNT_2(8),CNT_2_T(8),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
CNT_2_T(8) <= ((CNT_2(8) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
OR (CNT_2(0) AND CNT_2(1) AND CNT_2(2) AND CNT_2(3) AND
CNT_2(4) AND CNT_2(5) AND CNT_2(6) AND CNT_2(7) AND
$OpTx$BUF_OUT_CNT_2_INV$424));
FTCPE_CNT_29: FTCPE port map (CNT_2(9),CNT_2_T(9),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
CNT_2_T(9) <= ((CNT_2(9) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
OR (CNT_2(0) AND CNT_2(1) AND CNT_2(2) AND CNT_2(3) AND
CNT_2(4) AND CNT_2(5) AND CNT_2(6) AND CNT_2(7) AND CNT_2(8) AND
$OpTx$BUF_OUT_CNT_2_INV$424));
FTCPE_CNT_210: FTCPE port map (CNT_2(10),CNT_2_T(10),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
CNT_2_T(10) <= ((CNT_2(10) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
OR (CNT_2(0) AND CNT_2(1) AND CNT_2(2) AND CNT_2(3) AND
CNT_2(4) AND CNT_2(5) AND CNT_2(6) AND CNT_2(7) AND CNT_2(8) AND
CNT_2(9) AND $OpTx$BUF_OUT_CNT_2_INV$424));
FTCPE_CNT_211: FTCPE port map (CNT_2(11),CNT_2_T(11),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
CNT_2_T(11) <= ((CNT_2(11) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
OR (CNT_2(0) AND CNT_2(10) AND CNT_2(1) AND CNT_2(2) AND
CNT_2(3) AND CNT_2(4) AND CNT_2(5) AND CNT_2(6) AND CNT_2(7) AND
CNT_2(8) AND CNT_2(9) AND $OpTx$BUF_OUT_CNT_2_INV$424));
FTCPE_CNT_212: FTCPE port map (CNT_2(12),CNT_2_T(12),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
CNT_2_T(12) <= ((CNT_2(12) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
OR (CNT_2(0) AND CNT_2(10) AND CNT_2(11) AND CNT_2(1) AND
CNT_2(2) AND CNT_2(3) AND CNT_2(4) AND CNT_2(5) AND CNT_2(6) AND
CNT_2(7) AND CNT_2(8) AND CNT_2(9) AND
$OpTx$BUF_OUT_CNT_2_INV$424));
FDCPE_CNT_213: FDCPE port map (CNT_2(13),CNT_2_D(13),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
CNT_2_D(13) <= ((CNT_1(1).EXP)
OR (REG_CMP(2) AND CNT_2(13) AND NOT CNT_2(2) AND
NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
OR (NOT REG_CMP(2) AND CNT_2(13) AND CNT_2(2) AND
NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
OR (REG_CMP(4) AND CNT_2(13) AND NOT CNT_2(4) AND
NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
OR (REG_CMP(6) AND CNT_2(13) AND NOT CNT_2(6) AND
NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
OR (NOT REG_CMP(6) AND CNT_2(13) AND CNT_2(6) AND
NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
OR (EXP13_.EXP)
OR (REG_CMP(1) AND CNT_2(13) AND NOT CNT_2(1) AND
NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
OR (NOT REG_CMP(1) AND CNT_2(13) AND CNT_2(1) AND
NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
OR (REG_CMP(3) AND CNT_2(13) AND NOT CNT_2(3) AND
NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
OR (NOT REG_CMP(3) AND CNT_2(13) AND CNT_2(3) AND
NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
OR (NOT REG_CMP(4) AND CNT_2(13) AND CNT_2(4) AND
NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
OR (NOT REG_CMP(13) AND CNT_2(13) AND
NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
OR (CNT_2(13) AND $OpTx$INV$34 AND
NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
OR (REG_CMP(7) AND CNT_2(13) AND NOT CNT_2(7) AND
NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
OR (NOT REG_CMP(7) AND CNT_2(13) AND CNT_2(7) AND
NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2));
FTCPE_CNT_214: FTCPE port map (CNT_2(14),CNT_2_T(14),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
CNT_2_T(14) <= ((CNT_2(14) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
OR (CNT_2(0) AND CNT_2(10) AND CNT_2(11) AND CNT_2(12) AND
CNT_2(13) AND CNT_2(1) AND CNT_2(2) AND CNT_2(3) AND CNT_2(4) AND
CNT_2(5) AND CNT_2(6) AND CNT_2(7) AND CNT_2(8) AND CNT_2(9) AND
$OpTx$BUF_OUT_CNT_2_INV$424));
FTCPE_CNT_215: FTCPE port map (CNT_2(15),CNT_2_T(15),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
CNT_2_T(15) <= ((CNT_2(15) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
OR (CNT_2(0) AND CNT_2(10) AND CNT_2(11) AND CNT_2(12) AND
CNT_2(13) AND CNT_2(14) AND CNT_2(1) AND CNT_2(2) AND CNT_2(3) AND
CNT_2(4) AND CNT_2(5) AND CNT_2(6) AND CNT_2(7) AND CNT_2(8) AND
CNT_2(9) AND $OpTx$BUF_OUT_CNT_2_INV$424));
CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2 <= (CNT_2(0) AND CNT_2(10) AND CNT_2(11) AND CNT_2(12) AND
CNT_2(13) AND CNT_2(1) AND CNT_2(2) AND CNT_2(3) AND CNT_2(4) AND
CNT_2(5) AND CNT_2(6) AND CNT_2(7) AND CNT_2(8) AND CNT_2(9));
FIFO_CLK <= ((NOT REG_DIV(2) AND SER_GATE AND OUT_CNT_2)
OR (NOT REG_DIV(1) AND SER_GATE AND OUT_CNT_2)
OR (NOT REG_DIV(0) AND SER_GATE AND OUT_CNT_2)
OR (REG_DIV(3) AND SER_GATE AND OUT_CNT_2)
OR (REG_DIV(2) AND REG_DIV(1) AND REG_DIV(0) AND
NOT REG_DIV(3) AND SER_GATE AND CLK));
FDCPE_OUT_CNT_2: FDCPE port map (OUT_CNT_2,OUT_CNT_2_D,OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
OUT_CNT_2_D <= (($OpTx$INV$34)
OR (EXP11_.EXP)
OR (REG_CMP(13) AND NOT CNT_2(13))
OR (NOT REG_CMP(13) AND CNT_2(13))
OR (REG_CMP(1) AND NOT CNT_2(1))
OR (NOT REG_CMP(1) AND CNT_2(1))
OR (NOT REG_CMP(3) AND CNT_2(3))
OR (REG_CMP(7) AND NOT CNT_2(7))
OR (NOT REG_CMP(7) AND CNT_2(7)));
OUT_CNT_2/OUT_CNT_2_CLKF <= ((REG_DIV(2) AND OUT_TMP)
OR (REG_DIV(1) AND OUT_TMP)
OR (REG_DIV(0) AND OUT_TMP)
OR (REG_DIV(3) AND OUT_TMP)
OR (NOT REG_DIV(2) AND NOT REG_DIV(1) AND NOT REG_DIV(0) AND
NOT REG_DIV(3) AND CLK));
FDCPE_OUT_TMP: FDCPE port map (OUT_TMP,OUT_TMP_D,CLK,'0','0');
OUT_TMP_D <= ((REG_DIV(2) AND NOT REG_DIV(1) AND REG_DIV(0) AND
NOT REG_DIV(3) AND CNT_1(4))
OR (REG_DIV(2) AND NOT REG_DIV(1) AND NOT REG_DIV(0) AND
NOT REG_DIV(3) AND CNT_1(3))
OR (NOT REG_DIV(2) AND REG_DIV(1) AND REG_DIV(0) AND
NOT REG_DIV(3) AND CNT_1(2))
OR (NOT REG_DIV(2) AND NOT REG_DIV(1) AND REG_DIV(0) AND
NOT REG_DIV(3) AND CNT_1(0))
OR (REG_DIV(3) AND OUT_TMP)
OR (REG_DIV(2) AND REG_DIV(1) AND REG_DIV(0) AND OUT_TMP)
OR (NOT REG_DIV(2) AND NOT REG_DIV(1) AND NOT REG_DIV(0) AND OUT_TMP)
OR (REG_DIV(2) AND REG_DIV(1) AND NOT REG_DIV(0) AND
NOT REG_DIV(3) AND CNT_1(5))
OR (NOT REG_DIV(2) AND REG_DIV(1) AND NOT REG_DIV(0) AND
NOT REG_DIV(3) AND UC_CLK));
FDCPE_REG_CMP0: FDCPE port map (REG_CMP(0),SER_DATA.PIN,NOT SER_CLK,'0','0',REG_CMP_CE(0));
REG_CMP_CE(0) <= (SER_RDWR AND NOT SER_EN);
FDCPE_REG_CMP1: FDCPE port map (REG_CMP(1),REG_CMP(0),NOT SER_CLK,'0','0',REG_CMP_CE(1));
REG_CMP_CE(1) <= (SER_RDWR AND NOT SER_EN);
FDCPE_REG_CMP2: FDCPE port map (REG_CMP(2),REG_CMP(1),NOT SER_CLK,'0','0',REG_CMP_CE(2));
REG_CMP_CE(2) <= (SER_RDWR AND NOT SER_EN);
FDCPE_REG_CMP3: FDCPE port map (REG_CMP(3),REG_CMP(2),NOT SER_CLK,'0','0',REG_CMP_CE(3));
REG_CMP_CE(3) <= (SER_RDWR AND NOT SER_EN);
FDCPE_REG_CMP4: FDCPE port map (REG_CMP(4),REG_CMP(3),NOT SER_CLK,'0','0',REG_CMP_CE(4));
REG_CMP_CE(4) <= (SER_RDWR AND NOT SER_EN);
FDCPE_REG_CMP5: FDCPE port map (REG_CMP(5),REG_CMP(4),NOT SER_CLK,'0','0',REG_CMP_CE(5));
REG_CMP_CE(5) <= (SER_RDWR AND NOT SER_EN);
FDCPE_REG_CMP6: FDCPE port map (REG_CMP(6),REG_CMP(5),NOT SER_CLK,'0','0',REG_CMP_CE(6));
REG_CMP_CE(6) <= (SER_RDWR AND NOT SER_EN);
FDCPE_REG_CMP7: FDCPE port map (REG_CMP(7),REG_CMP(6),NOT SER_CLK,'0','0',REG_CMP_CE(7));
REG_CMP_CE(7) <= (SER_RDWR AND NOT SER_EN);
FDCPE_REG_CMP8: FDCPE port map (REG_CMP(8),REG_CMP(7),NOT SER_CLK,'0','0',REG_CMP_CE(8));
REG_CMP_CE(8) <= (SER_RDWR AND NOT SER_EN);
FDCPE_REG_CMP9: FDCPE port map (REG_CMP(9),REG_CMP(8),NOT SER_CLK,'0','0',REG_CMP_CE(9));
REG_CMP_CE(9) <= (SER_RDWR AND NOT SER_EN);
FDCPE_REG_CMP10: FDCPE port map (REG_CMP(10),REG_CMP(9),NOT SER_CLK,'0','0',REG_CMP_CE(10));
REG_CMP_CE(10) <= (SER_RDWR AND NOT SER_EN);
FDCPE_REG_CMP11: FDCPE port map (REG_CMP(11),REG_CMP(10),NOT SER_CLK,'0','0',REG_CMP_CE(11));
REG_CMP_CE(11) <= (SER_RDWR AND NOT SER_EN);
FDCPE_REG_CMP12: FDCPE port map (REG_CMP(12),REG_CMP(11),NOT SER_CLK,'0','0',REG_CMP_CE(12));
REG_CMP_CE(12) <= (SER_RDWR AND NOT SER_EN);
FDCPE_REG_CMP13: FDCPE port map (REG_CMP(13),REG_CMP(12),NOT SER_CLK,'0','0',REG_CMP_CE(13));
REG_CMP_CE(13) <= (SER_RDWR AND NOT SER_EN);
FDCPE_REG_CMP14: FDCPE port map (REG_CMP(14),REG_CMP(13),NOT SER_CLK,'0','0',REG_CMP_CE(14));
REG_CMP_CE(14) <= (SER_RDWR AND NOT SER_EN);
FDCPE_REG_CMP15: FDCPE port map (REG_CMP(15),REG_CMP(14),NOT SER_CLK,'0','0',REG_CMP_CE(15));
REG_CMP_CE(15) <= (SER_RDWR AND NOT SER_EN);
FDCPE_REG_DIV0: FDCPE port map (REG_DIV(0),REG_CMP(15),NOT SER_CLK,'0','0',REG_DIV_CE(0));
REG_DIV_CE(0) <= (SER_RDWR AND NOT SER_EN);
FDCPE_REG_DIV1: FDCPE port map (REG_DIV(1),REG_DIV(0),NOT SER_CLK,'0','0',REG_DIV_CE(1));
REG_DIV_CE(1) <= (SER_RDWR AND NOT SER_EN);
FDCPE_REG_DIV2: FDCPE port map (REG_DIV(2),REG_DIV(1),NOT SER_CLK,'0','0',REG_DIV_CE(2));
REG_DIV_CE(2) <= (SER_RDWR AND NOT SER_EN);
FDCPE_REG_DIV3: FDCPE port map (REG_DIV(3),REG_DIV(2),NOT SER_CLK,'0','0',REG_DIV_CE(3));
REG_DIV_CE(3) <= (SER_RDWR AND NOT SER_EN);
FDCPE_REG_KEY0: FDCPE port map (REG_KEY(0),REG_KEY_D(0),NOT SER_CLK,REG_KEY_CLR(0),REG_KEY_PRE(0));
REG_KEY_D(0) <= (SER_RDWR AND REG_KEY(0));
REG_KEY_CLR(0) <= (SER_EN AND NOT DIN_SV5(0));
REG_KEY_PRE(0) <= (SER_EN AND DIN_SV5(0));
FDCPE_REG_KEY1: FDCPE port map (REG_KEY(1),REG_KEY_D(1),NOT SER_CLK,REG_KEY_CLR(1),REG_KEY_PRE(1));
REG_KEY_D(1) <= ((SER_RDWR AND REG_KEY(1))
OR (NOT SER_RDWR AND REG_KEY(0)));
REG_KEY_CLR(1) <= (SER_EN AND NOT DIN_SV5(1));
REG_KEY_PRE(1) <= (SER_EN AND DIN_SV5(1));
FDCPE_REG_KEY2: FDCPE port map (REG_KEY(2),REG_KEY_D(2),NOT SER_CLK,REG_KEY_CLR(2),REG_KEY_PRE(2));
REG_KEY_D(2) <= ((SER_RDWR AND REG_KEY(2))
OR (NOT SER_RDWR AND REG_KEY(1)));
REG_KEY_CLR(2) <= (SER_EN AND NOT DIN_SV5(2));
REG_KEY_PRE(2) <= (SER_EN AND DIN_SV5(2));
FDCPE_REG_KEY3: FDCPE port map (REG_KEY(3),REG_KEY_D(3),NOT SER_CLK,REG_KEY_CLR(3),REG_KEY_PRE(3));
REG_KEY_D(3) <= ((SER_RDWR AND REG_KEY(3))
OR (NOT SER_RDWR AND REG_KEY(2)));
REG_KEY_CLR(3) <= (SER_EN AND NOT DIN_SV5(3));
REG_KEY_PRE(3) <= (SER_EN AND DIN_SV5(3));
FDCPE_REG_KEY4: FDCPE port map (REG_KEY(4),REG_KEY_D(4),NOT SER_CLK,REG_KEY_CLR(4),REG_KEY_PRE(4));
REG_KEY_D(4) <= ((SER_RDWR AND REG_KEY(4))
OR (NOT SER_RDWR AND REG_KEY(3)));
REG_KEY_CLR(4) <= (SER_EN AND NOT DIN_SV5(4));
REG_KEY_PRE(4) <= (SER_EN AND DIN_SV5(4));
FDCPE_REG_KEY5: FDCPE port map (REG_KEY(5),REG_KEY_D(5),NOT SER_CLK,REG_KEY_CLR(5),REG_KEY_PRE(5));
REG_KEY_D(5) <= ((SER_RDWR AND REG_KEY(5))
OR (NOT SER_RDWR AND REG_KEY(4)));
REG_KEY_CLR(5) <= (SER_EN AND NOT DIN_SV5(5));
REG_KEY_PRE(5) <= (SER_EN AND DIN_SV5(5));
FDCPE_REG_KEY6: FDCPE port map (REG_KEY(6),REG_KEY_D(6),NOT SER_CLK,REG_KEY_CLR(6),REG_KEY_PRE(6));
REG_KEY_D(6) <= ((SER_RDWR AND REG_KEY(6))
OR (NOT SER_RDWR AND REG_KEY(5)));
REG_KEY_CLR(6) <= (SER_EN AND NOT DIN_SV5(6));
REG_KEY_PRE(6) <= (SER_EN AND DIN_SV5(6));
FDCPE_REG_KEY7: FDCPE port map (REG_KEY(7),REG_KEY_D(7),NOT SER_CLK,REG_KEY_CLR(7),REG_KEY_PRE(7));
REG_KEY_D(7) <= ((SER_RDWR AND REG_KEY(7))
OR (NOT SER_RDWR AND REG_KEY(6)));
REG_KEY_CLR(7) <= (SER_EN AND NOT DIN_SV5(7));
REG_KEY_PRE(7) <= (SER_EN AND DIN_SV5(7));
FDCPE_SER_DATA: FDCPE port map (SER_DATA_I,REG_KEY(7),NOT SER_CLK,'0','0',SER_DATA_CE);
SER_DATA_CE <= (NOT SER_RDWR AND NOT SER_EN);
SER_DATA <= SER_DATA_I when SER_DATA_OE = '1' else 'Z';
SER_DATA_OE <= (NOT SER_RDWR AND NOT SER_EN);
FTCPE_TST_LED: FTCPE port map (TST_LED,TST_LED_T,CLK,'0','0');
TST_LED_T <= (UC_CLK AND CNT_1(0) AND CNT_1(2) AND CNT_1(3) AND
CNT_1(4) AND CNT_1(5) AND CNT_1(6));
FTCPE_UC_CLK: FTCPE port map (UC_CLK,CNT_1(0),CLK,'0','0');
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC9572XL-10-VQ44
--------------------------------
/44 43 42 41 40 39 38 37 36 35 34 \
| 1 33 |
| 2 32 |
| 3 31 |
| 4 30 |
| 5 XC9572XL-10-VQ44 29 |
| 6 28 |
| 7 27 |
| 8 26 |
| 9 25 |
| 10 24 |
| 11 23 |
\ 12 13 14 15 16 17 18 19 20 21 22 /
--------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 KPR 23 DIN_SV5<2>
2 SER_DATA 24 TDO
3 DIN_SV5<6> 25 GND
4 GND 26 VCC
5 KPR 27 KPR
6 SER_EN 28 DIN_SV5<7>
7 KPR 29 UC_CLK
8 KPR 30 DIN_SV5<4>
9 TDI 31 SER_GATE
10 TMS 32 TST_LED
11 TCK 33 KPR
12 DIN_SV5<5> 34 KPR
13 DIN_SV5<1> 35 VCC
14 KPR 36 KPR
15 VCC 37 KPR
16 KPR 38 SER_RDWR
17 GND 39 FIFO_CLK
18 KPR 40 DIN_SV5<0>
19 KPR 41 ADC_CLK
20 KPR 42 KPR
21 KPR 43 CLK
22 DIN_SV5<3> 44 SER_CLK
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc9572xl-10-VQ44
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 25