Equations

********** Mapped Logic **********

$OpTx$BUF_OUT_CNT_2_INV$424 <= (($OpTx$INV$34)
      OR (CNT_1(7).EXP)
      OR (REG_CMP(13) AND NOT CNT_2(13))
      OR (NOT REG_CMP(13) AND CNT_2(13))
      OR (REG_CMP(3) AND NOT CNT_2(3))
      OR (NOT REG_CMP(3) AND CNT_2(3))
      OR (NOT REG_CMP(4) AND CNT_2(4))
      OR (REG_CMP(2) AND NOT CNT_2(2))
      OR (NOT REG_CMP(2) AND CNT_2(2))
      OR (REG_CMP(4) AND NOT CNT_2(4))
      OR (REG_CMP(6) AND NOT CNT_2(6))
      OR (NOT REG_CMP(6) AND CNT_2(6))
      OR (REG_CMP(1) AND NOT CNT_2(1))
      OR (NOT REG_CMP(1) AND CNT_2(1))
      OR (REG_CMP(7) AND NOT CNT_2(7))
      OR (NOT REG_CMP(7) AND CNT_2(7)));

$OpTx$INV$34 <= ((REG_CMP(12) AND NOT CNT_2(12))
      OR (NOT REG_CMP(12) AND CNT_2(12))
      OR (REG_CMP(15) AND NOT CNT_2(15))
      OR (NOT REG_CMP(15) AND CNT_2(15))
      OR (CNT_2(10).EXP)
      OR (REG_CMP(14) AND NOT CNT_2(14))
      OR (NOT REG_CMP(14) AND CNT_2(14))
      OR (REG_CMP(5) AND NOT CNT_2(5))
      OR (REG_CMP(8) AND NOT CNT_2(8))
      OR (NOT REG_CMP(8) AND CNT_2(8))
      OR (REG_CMP(10) AND NOT CNT_2(10))
      OR (NOT REG_CMP(10) AND CNT_2(10))
      OR (REG_CMP(11) AND NOT CNT_2(11))
      OR (NOT REG_CMP(11) AND CNT_2(11))
      OR (NOT REG_CMP(5) AND CNT_2(5)));

ADC_CLK <= NOT (((NOT REG_DIV(2) AND SER_GATE AND OUT_CNT_2)
      OR (NOT REG_DIV(1) AND SER_GATE AND OUT_CNT_2)
      OR (NOT REG_DIV(0) AND SER_GATE AND OUT_CNT_2)
      OR (REG_DIV(3) AND SER_GATE AND OUT_CNT_2)
      OR (REG_DIV(2) AND REG_DIV(1) AND REG_DIV(0) AND
      NOT REG_DIV(3) AND SER_GATE AND CLK)));

FTCPE_CNT_10: FTCPE port map (CNT_1(0),'1',CLK,'0','0');

FTCPE_CNT_12: FTCPE port map (CNT_1(2),CNT_1_T(2),CLK,'0','0');
CNT_1_T(2) <= (UC_CLK AND CNT_1(0));

FTCPE_CNT_13: FTCPE port map (CNT_1(3),CNT_1_T(3),CLK,'0','0');
CNT_1_T(3) <= (UC_CLK AND CNT_1(0) AND CNT_1(2));

FTCPE_CNT_14: FTCPE port map (CNT_1(4),CNT_1_T(4),CLK,'0','0');
CNT_1_T(4) <= (UC_CLK AND CNT_1(0) AND CNT_1(2) AND CNT_1(3));

FTCPE_CNT_15: FTCPE port map (CNT_1(5),CNT_1_T(5),CLK,'0','0');
CNT_1_T(5) <= (UC_CLK AND CNT_1(0) AND CNT_1(2) AND CNT_1(3) AND
CNT_1(4));

FTCPE_CNT_16: FTCPE port map (CNT_1(6),CNT_1_T(6),CLK,'0','0');
CNT_1_T(6) <= (UC_CLK AND CNT_1(0) AND CNT_1(2) AND CNT_1(3) AND
CNT_1(4) AND CNT_1(5));

FDCPE_CNT_20: FDCPE port map (CNT_2(0),CNT_2_D(0),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
     CNT_2_D(0) <= ((REG_CMP(13) AND NOT CNT_2(0) AND NOT CNT_2(13))
      OR (NOT REG_CMP(13) AND NOT CNT_2(0) AND CNT_2(13))
      OR (REG_CMP(1) AND NOT CNT_2(0) AND NOT CNT_2(1))
      OR (NOT REG_CMP(1) AND NOT CNT_2(0) AND CNT_2(1))
      OR (CNT_1(3).EXP)
      OR (REG_CMP(3) AND NOT CNT_2(0) AND NOT CNT_2(3))
      OR (NOT REG_CMP(3) AND NOT CNT_2(0) AND CNT_2(3))
      OR (REG_CMP(4) AND NOT CNT_2(0) AND NOT CNT_2(4))
      OR (NOT REG_CMP(4) AND NOT CNT_2(0) AND CNT_2(4))
      OR (NOT REG_CMP(6) AND NOT CNT_2(0) AND CNT_2(6))
      OR (REG_CMP(0) AND NOT CNT_2(0))
      OR (NOT CNT_2(0) AND $OpTx$INV$34)
      OR (REG_CMP(7) AND NOT CNT_2(0) AND NOT CNT_2(7))
      OR (NOT REG_CMP(7) AND NOT CNT_2(0) AND CNT_2(7)));

FDCPE_CNT_21: FDCPE port map (CNT_2(1),CNT_2_D(1),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
     CNT_2_D(1) <= ((CNT_2(0) AND NOT CNT_2(1) AND
      $OpTx$BUF_OUT_CNT_2_INV$424)
      OR (NOT CNT_2(0) AND CNT_2(1) AND
      $OpTx$BUF_OUT_CNT_2_INV$424));

FTCPE_CNT_22: FTCPE port map (CNT_2(2),CNT_2_T(2),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
     CNT_2_T(2) <= ((CNT_2(2) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
      OR (CNT_2(0) AND CNT_2(1) AND
      $OpTx$BUF_OUT_CNT_2_INV$424));

FTCPE_CNT_23: FTCPE port map (CNT_2(3),CNT_2_T(3),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
     CNT_2_T(3) <= ((CNT_2(3) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
      OR (CNT_2(0) AND CNT_2(1) AND CNT_2(2) AND
      $OpTx$BUF_OUT_CNT_2_INV$424));

FTCPE_CNT_24: FTCPE port map (CNT_2(4),CNT_2_T(4),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
     CNT_2_T(4) <= ((CNT_2(4) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
      OR (CNT_2(0) AND CNT_2(1) AND CNT_2(2) AND CNT_2(3) AND
      $OpTx$BUF_OUT_CNT_2_INV$424));

FTCPE_CNT_25: FTCPE port map (CNT_2(5),CNT_2_T(5),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
     CNT_2_T(5) <= ((CNT_2(5) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
      OR (CNT_2(0) AND CNT_2(1) AND CNT_2(2) AND CNT_2(3) AND
      CNT_2(4) AND $OpTx$BUF_OUT_CNT_2_INV$424));

FTCPE_CNT_26: FTCPE port map (CNT_2(6),CNT_2_T(6),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
     CNT_2_T(6) <= ((CNT_2(6) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
      OR (CNT_2(0) AND CNT_2(1) AND CNT_2(2) AND CNT_2(3) AND
      CNT_2(4) AND CNT_2(5) AND $OpTx$BUF_OUT_CNT_2_INV$424));

FTCPE_CNT_27: FTCPE port map (CNT_2(7),CNT_2_T(7),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
     CNT_2_T(7) <= ((CNT_2(7) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
      OR (CNT_2(0) AND CNT_2(1) AND CNT_2(2) AND CNT_2(3) AND
      CNT_2(4) AND CNT_2(5) AND CNT_2(6) AND
      $OpTx$BUF_OUT_CNT_2_INV$424));

FTCPE_CNT_28: FTCPE port map (CNT_2(8),CNT_2_T(8),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
     CNT_2_T(8) <= ((CNT_2(8) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
      OR (CNT_2(0) AND CNT_2(1) AND CNT_2(2) AND CNT_2(3) AND
      CNT_2(4) AND CNT_2(5) AND CNT_2(6) AND CNT_2(7) AND
      $OpTx$BUF_OUT_CNT_2_INV$424));

FTCPE_CNT_29: FTCPE port map (CNT_2(9),CNT_2_T(9),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
     CNT_2_T(9) <= ((CNT_2(9) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
      OR (CNT_2(0) AND CNT_2(1) AND CNT_2(2) AND CNT_2(3) AND
      CNT_2(4) AND CNT_2(5) AND CNT_2(6) AND CNT_2(7) AND CNT_2(8) AND
      $OpTx$BUF_OUT_CNT_2_INV$424));

FTCPE_CNT_210: FTCPE port map (CNT_2(10),CNT_2_T(10),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
     CNT_2_T(10) <= ((CNT_2(10) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
      OR (CNT_2(0) AND CNT_2(1) AND CNT_2(2) AND CNT_2(3) AND
      CNT_2(4) AND CNT_2(5) AND CNT_2(6) AND CNT_2(7) AND CNT_2(8) AND
      CNT_2(9) AND $OpTx$BUF_OUT_CNT_2_INV$424));

FTCPE_CNT_211: FTCPE port map (CNT_2(11),CNT_2_T(11),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
     CNT_2_T(11) <= ((CNT_2(11) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
      OR (CNT_2(0) AND CNT_2(10) AND CNT_2(1) AND CNT_2(2) AND
      CNT_2(3) AND CNT_2(4) AND CNT_2(5) AND CNT_2(6) AND CNT_2(7) AND
      CNT_2(8) AND CNT_2(9) AND $OpTx$BUF_OUT_CNT_2_INV$424));

FTCPE_CNT_212: FTCPE port map (CNT_2(12),CNT_2_T(12),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
     CNT_2_T(12) <= ((CNT_2(12) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
      OR (CNT_2(0) AND CNT_2(10) AND CNT_2(11) AND CNT_2(1) AND
      CNT_2(2) AND CNT_2(3) AND CNT_2(4) AND CNT_2(5) AND CNT_2(6) AND
      CNT_2(7) AND CNT_2(8) AND CNT_2(9) AND
      $OpTx$BUF_OUT_CNT_2_INV$424));

FDCPE_CNT_213: FDCPE port map (CNT_2(13),CNT_2_D(13),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
     CNT_2_D(13) <= ((CNT_1(1).EXP)
      OR (REG_CMP(2) AND CNT_2(13) AND NOT CNT_2(2) AND
      NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
      OR (NOT REG_CMP(2) AND CNT_2(13) AND CNT_2(2) AND
      NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
      OR (REG_CMP(4) AND CNT_2(13) AND NOT CNT_2(4) AND
      NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
      OR (REG_CMP(6) AND CNT_2(13) AND NOT CNT_2(6) AND
      NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
      OR (NOT REG_CMP(6) AND CNT_2(13) AND CNT_2(6) AND
      NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
      OR (EXP13_.EXP)
      OR (REG_CMP(1) AND CNT_2(13) AND NOT CNT_2(1) AND
      NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
      OR (NOT REG_CMP(1) AND CNT_2(13) AND CNT_2(1) AND
      NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
      OR (REG_CMP(3) AND CNT_2(13) AND NOT CNT_2(3) AND
      NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
      OR (NOT REG_CMP(3) AND CNT_2(13) AND CNT_2(3) AND
      NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
      OR (NOT REG_CMP(4) AND CNT_2(13) AND CNT_2(4) AND
      NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
      OR (NOT REG_CMP(13) AND CNT_2(13) AND
      NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
      OR (CNT_2(13) AND $OpTx$INV$34 AND
      NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
      OR (REG_CMP(7) AND CNT_2(13) AND NOT CNT_2(7) AND
      NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2)
      OR (NOT REG_CMP(7) AND CNT_2(13) AND CNT_2(7) AND
      NOT CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2));

FTCPE_CNT_214: FTCPE port map (CNT_2(14),CNT_2_T(14),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
     CNT_2_T(14) <= ((CNT_2(14) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
      OR (CNT_2(0) AND CNT_2(10) AND CNT_2(11) AND CNT_2(12) AND
      CNT_2(13) AND CNT_2(1) AND CNT_2(2) AND CNT_2(3) AND CNT_2(4) AND
      CNT_2(5) AND CNT_2(6) AND CNT_2(7) AND CNT_2(8) AND CNT_2(9) AND
      $OpTx$BUF_OUT_CNT_2_INV$424));

FTCPE_CNT_215: FTCPE port map (CNT_2(15),CNT_2_T(15),OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
     CNT_2_T(15) <= ((CNT_2(15) AND NOT $OpTx$BUF_OUT_CNT_2_INV$424)
      OR (CNT_2(0) AND CNT_2(10) AND CNT_2(11) AND CNT_2(12) AND
      CNT_2(13) AND CNT_2(14) AND CNT_2(1) AND CNT_2(2) AND CNT_2(3) AND
      CNT_2(4) AND CNT_2(5) AND CNT_2(6) AND CNT_2(7) AND CNT_2(8) AND
      CNT_2(9) AND $OpTx$BUF_OUT_CNT_2_INV$424));

CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2 <= (CNT_2(0) AND CNT_2(10) AND CNT_2(11) AND CNT_2(12) AND
CNT_2(13) AND CNT_2(1) AND CNT_2(2) AND CNT_2(3) AND CNT_2(4) AND
CNT_2(5) AND CNT_2(6) AND CNT_2(7) AND CNT_2(8) AND CNT_2(9));

FIFO_CLK <= ((NOT REG_DIV(2) AND SER_GATE AND OUT_CNT_2)
      OR (NOT REG_DIV(1) AND SER_GATE AND OUT_CNT_2)
      OR (NOT REG_DIV(0) AND SER_GATE AND OUT_CNT_2)
      OR (REG_DIV(3) AND SER_GATE AND OUT_CNT_2)
      OR (REG_DIV(2) AND REG_DIV(1) AND REG_DIV(0) AND
      NOT REG_DIV(3) AND SER_GATE AND CLK));

FDCPE_OUT_CNT_2: FDCPE port map (OUT_CNT_2,OUT_CNT_2_D,OUT_CNT_2/OUT_CNT_2_CLKF,'0','0');
     OUT_CNT_2_D <= (($OpTx$INV$34)
      OR (EXP11_.EXP)
      OR (REG_CMP(13) AND NOT CNT_2(13))
      OR (NOT REG_CMP(13) AND CNT_2(13))
      OR (REG_CMP(1) AND NOT CNT_2(1))
      OR (NOT REG_CMP(1) AND CNT_2(1))
      OR (NOT REG_CMP(3) AND CNT_2(3))
      OR (REG_CMP(7) AND NOT CNT_2(7))
      OR (NOT REG_CMP(7) AND CNT_2(7)));

OUT_CNT_2/OUT_CNT_2_CLKF <= ((REG_DIV(2) AND OUT_TMP)
      OR (REG_DIV(1) AND OUT_TMP)
      OR (REG_DIV(0) AND OUT_TMP)
      OR (REG_DIV(3) AND OUT_TMP)
      OR (NOT REG_DIV(2) AND NOT REG_DIV(1) AND NOT REG_DIV(0) AND
      NOT REG_DIV(3) AND CLK));

FDCPE_OUT_TMP: FDCPE port map (OUT_TMP,OUT_TMP_D,CLK,'0','0');
     OUT_TMP_D <= ((REG_DIV(2) AND NOT REG_DIV(1) AND REG_DIV(0) AND
      NOT REG_DIV(3) AND CNT_1(4))
      OR (REG_DIV(2) AND NOT REG_DIV(1) AND NOT REG_DIV(0) AND
      NOT REG_DIV(3) AND CNT_1(3))
      OR (NOT REG_DIV(2) AND REG_DIV(1) AND REG_DIV(0) AND
      NOT REG_DIV(3) AND CNT_1(2))
      OR (NOT REG_DIV(2) AND NOT REG_DIV(1) AND REG_DIV(0) AND
      NOT REG_DIV(3) AND CNT_1(0))
      OR (REG_DIV(3) AND OUT_TMP)
      OR (REG_DIV(2) AND REG_DIV(1) AND REG_DIV(0) AND OUT_TMP)
      OR (NOT REG_DIV(2) AND NOT REG_DIV(1) AND NOT REG_DIV(0) AND OUT_TMP)
      OR (REG_DIV(2) AND REG_DIV(1) AND NOT REG_DIV(0) AND
      NOT REG_DIV(3) AND CNT_1(5))
      OR (NOT REG_DIV(2) AND REG_DIV(1) AND NOT REG_DIV(0) AND
      NOT REG_DIV(3) AND UC_CLK));

FDCPE_REG_CMP0: FDCPE port map (REG_CMP(0),SER_DATA.PIN,NOT SER_CLK,'0','0',REG_CMP_CE(0));
REG_CMP_CE(0) <= (SER_RDWR AND NOT SER_EN);

FDCPE_REG_CMP1: FDCPE port map (REG_CMP(1),REG_CMP(0),NOT SER_CLK,'0','0',REG_CMP_CE(1));
REG_CMP_CE(1) <= (SER_RDWR AND NOT SER_EN);

FDCPE_REG_CMP2: FDCPE port map (REG_CMP(2),REG_CMP(1),NOT SER_CLK,'0','0',REG_CMP_CE(2));
REG_CMP_CE(2) <= (SER_RDWR AND NOT SER_EN);

FDCPE_REG_CMP3: FDCPE port map (REG_CMP(3),REG_CMP(2),NOT SER_CLK,'0','0',REG_CMP_CE(3));
REG_CMP_CE(3) <= (SER_RDWR AND NOT SER_EN);

FDCPE_REG_CMP4: FDCPE port map (REG_CMP(4),REG_CMP(3),NOT SER_CLK,'0','0',REG_CMP_CE(4));
REG_CMP_CE(4) <= (SER_RDWR AND NOT SER_EN);

FDCPE_REG_CMP5: FDCPE port map (REG_CMP(5),REG_CMP(4),NOT SER_CLK,'0','0',REG_CMP_CE(5));
REG_CMP_CE(5) <= (SER_RDWR AND NOT SER_EN);

FDCPE_REG_CMP6: FDCPE port map (REG_CMP(6),REG_CMP(5),NOT SER_CLK,'0','0',REG_CMP_CE(6));
REG_CMP_CE(6) <= (SER_RDWR AND NOT SER_EN);

FDCPE_REG_CMP7: FDCPE port map (REG_CMP(7),REG_CMP(6),NOT SER_CLK,'0','0',REG_CMP_CE(7));
REG_CMP_CE(7) <= (SER_RDWR AND NOT SER_EN);

FDCPE_REG_CMP8: FDCPE port map (REG_CMP(8),REG_CMP(7),NOT SER_CLK,'0','0',REG_CMP_CE(8));
REG_CMP_CE(8) <= (SER_RDWR AND NOT SER_EN);

FDCPE_REG_CMP9: FDCPE port map (REG_CMP(9),REG_CMP(8),NOT SER_CLK,'0','0',REG_CMP_CE(9));
REG_CMP_CE(9) <= (SER_RDWR AND NOT SER_EN);

FDCPE_REG_CMP10: FDCPE port map (REG_CMP(10),REG_CMP(9),NOT SER_CLK,'0','0',REG_CMP_CE(10));
REG_CMP_CE(10) <= (SER_RDWR AND NOT SER_EN);

FDCPE_REG_CMP11: FDCPE port map (REG_CMP(11),REG_CMP(10),NOT SER_CLK,'0','0',REG_CMP_CE(11));
REG_CMP_CE(11) <= (SER_RDWR AND NOT SER_EN);

FDCPE_REG_CMP12: FDCPE port map (REG_CMP(12),REG_CMP(11),NOT SER_CLK,'0','0',REG_CMP_CE(12));
REG_CMP_CE(12) <= (SER_RDWR AND NOT SER_EN);

FDCPE_REG_CMP13: FDCPE port map (REG_CMP(13),REG_CMP(12),NOT SER_CLK,'0','0',REG_CMP_CE(13));
REG_CMP_CE(13) <= (SER_RDWR AND NOT SER_EN);

FDCPE_REG_CMP14: FDCPE port map (REG_CMP(14),REG_CMP(13),NOT SER_CLK,'0','0',REG_CMP_CE(14));
REG_CMP_CE(14) <= (SER_RDWR AND NOT SER_EN);

FDCPE_REG_CMP15: FDCPE port map (REG_CMP(15),REG_CMP(14),NOT SER_CLK,'0','0',REG_CMP_CE(15));
REG_CMP_CE(15) <= (SER_RDWR AND NOT SER_EN);

FDCPE_REG_DIV0: FDCPE port map (REG_DIV(0),REG_CMP(15),NOT SER_CLK,'0','0',REG_DIV_CE(0));
REG_DIV_CE(0) <= (SER_RDWR AND NOT SER_EN);

FDCPE_REG_DIV1: FDCPE port map (REG_DIV(1),REG_DIV(0),NOT SER_CLK,'0','0',REG_DIV_CE(1));
REG_DIV_CE(1) <= (SER_RDWR AND NOT SER_EN);

FDCPE_REG_DIV2: FDCPE port map (REG_DIV(2),REG_DIV(1),NOT SER_CLK,'0','0',REG_DIV_CE(2));
REG_DIV_CE(2) <= (SER_RDWR AND NOT SER_EN);

FDCPE_REG_DIV3: FDCPE port map (REG_DIV(3),REG_DIV(2),NOT SER_CLK,'0','0',REG_DIV_CE(3));
REG_DIV_CE(3) <= (SER_RDWR AND NOT SER_EN);

FDCPE_REG_KEY0: FDCPE port map (REG_KEY(0),REG_KEY_D(0),NOT SER_CLK,REG_KEY_CLR(0),REG_KEY_PRE(0));
     REG_KEY_D(0) <= (SER_RDWR AND REG_KEY(0));
     REG_KEY_CLR(0) <= (SER_EN AND NOT DIN_SV5(0));
     REG_KEY_PRE(0) <= (SER_EN AND DIN_SV5(0));

FDCPE_REG_KEY1: FDCPE port map (REG_KEY(1),REG_KEY_D(1),NOT SER_CLK,REG_KEY_CLR(1),REG_KEY_PRE(1));
     REG_KEY_D(1) <= ((SER_RDWR AND REG_KEY(1))
      OR (NOT SER_RDWR AND REG_KEY(0)));
     REG_KEY_CLR(1) <= (SER_EN AND NOT DIN_SV5(1));
     REG_KEY_PRE(1) <= (SER_EN AND DIN_SV5(1));

FDCPE_REG_KEY2: FDCPE port map (REG_KEY(2),REG_KEY_D(2),NOT SER_CLK,REG_KEY_CLR(2),REG_KEY_PRE(2));
     REG_KEY_D(2) <= ((SER_RDWR AND REG_KEY(2))
      OR (NOT SER_RDWR AND REG_KEY(1)));
     REG_KEY_CLR(2) <= (SER_EN AND NOT DIN_SV5(2));
     REG_KEY_PRE(2) <= (SER_EN AND DIN_SV5(2));

FDCPE_REG_KEY3: FDCPE port map (REG_KEY(3),REG_KEY_D(3),NOT SER_CLK,REG_KEY_CLR(3),REG_KEY_PRE(3));
     REG_KEY_D(3) <= ((SER_RDWR AND REG_KEY(3))
      OR (NOT SER_RDWR AND REG_KEY(2)));
     REG_KEY_CLR(3) <= (SER_EN AND NOT DIN_SV5(3));
     REG_KEY_PRE(3) <= (SER_EN AND DIN_SV5(3));

FDCPE_REG_KEY4: FDCPE port map (REG_KEY(4),REG_KEY_D(4),NOT SER_CLK,REG_KEY_CLR(4),REG_KEY_PRE(4));
     REG_KEY_D(4) <= ((SER_RDWR AND REG_KEY(4))
      OR (NOT SER_RDWR AND REG_KEY(3)));
     REG_KEY_CLR(4) <= (SER_EN AND NOT DIN_SV5(4));
     REG_KEY_PRE(4) <= (SER_EN AND DIN_SV5(4));

FDCPE_REG_KEY5: FDCPE port map (REG_KEY(5),REG_KEY_D(5),NOT SER_CLK,REG_KEY_CLR(5),REG_KEY_PRE(5));
     REG_KEY_D(5) <= ((SER_RDWR AND REG_KEY(5))
      OR (NOT SER_RDWR AND REG_KEY(4)));
     REG_KEY_CLR(5) <= (SER_EN AND NOT DIN_SV5(5));
     REG_KEY_PRE(5) <= (SER_EN AND DIN_SV5(5));

FDCPE_REG_KEY6: FDCPE port map (REG_KEY(6),REG_KEY_D(6),NOT SER_CLK,REG_KEY_CLR(6),REG_KEY_PRE(6));
     REG_KEY_D(6) <= ((SER_RDWR AND REG_KEY(6))
      OR (NOT SER_RDWR AND REG_KEY(5)));
     REG_KEY_CLR(6) <= (SER_EN AND NOT DIN_SV5(6));
     REG_KEY_PRE(6) <= (SER_EN AND DIN_SV5(6));

FDCPE_REG_KEY7: FDCPE port map (REG_KEY(7),REG_KEY_D(7),NOT SER_CLK,REG_KEY_CLR(7),REG_KEY_PRE(7));
     REG_KEY_D(7) <= ((SER_RDWR AND REG_KEY(7))
      OR (NOT SER_RDWR AND REG_KEY(6)));
     REG_KEY_CLR(7) <= (SER_EN AND NOT DIN_SV5(7));
     REG_KEY_PRE(7) <= (SER_EN AND DIN_SV5(7));

FDCPE_SER_DATA: FDCPE port map (SER_DATA_I,REG_KEY(7),NOT SER_CLK,'0','0',SER_DATA_CE);
     SER_DATA_CE <= (NOT SER_RDWR AND NOT SER_EN);
     SER_DATA <= SER_DATA_I when SER_DATA_OE = '1' else 'Z';
     SER_DATA_OE <= (NOT SER_RDWR AND NOT SER_EN);

FTCPE_TST_LED: FTCPE port map (TST_LED,TST_LED_T,CLK,'0','0');
TST_LED_T <= (UC_CLK AND CNT_1(0) AND CNT_1(2) AND CNT_1(3) AND
CNT_1(4) AND CNT_1(5) AND CNT_1(6));

FTCPE_UC_CLK: FTCPE port map (UC_CLK,CNT_1(0),CLK,'0','0');