Logic

Signal Name Total Pterms Total Inputs Function Block Macrocell Power Mode Slew Rate Pin Number Pin Type Pin Use Reg Init State
REG_KEY<2> 4 5 FB1 MC14 STD   1 I/O/GCK3 (b) RESET
SER_DATA 3 3 FB1 MC15 STD FAST 2 I/O I/O RESET
OUT_CNT_2/OUT_CNT_2_CLKF 5 6 FB1 MC17 STD   3 I/O I  
CNT_2_Madd__add0000__and0012/CNT_2_Madd__add0000__and0012_D2 1 14 FB3 MC2 STD   5 I/O (b)  
CNT_2<8> 3 11 FB3 MC5 STD   6 I/O I RESET
CNT_2<5> 3 8 FB3 MC8 STD   7 I/O (b) RESET
CNT_2<4> 3 7 FB3 MC9 STD   8 I/O (b) RESET
CNT_2<2> 3 5 FB3 MC11 STD   12 I/O I RESET
CNT_2<14> 3 17 FB3 MC14 STD   13 I/O I RESET
CNT_2<12> 3 15 FB3 MC15 STD   14 I/O (b) RESET
CNT_2<10> 3 13 FB3 MC17 STD   16 I/O (b) RESET
CNT_2<11> 3 14 FB3 MC16 STD   18 I/O (b) RESET
REG_DIV<3> 2 3 FB4 MC2 STD   19 I/O (b) RESET
REG_CMP<8> 2 3 FB4 MC5 STD   20 I/O (b) RESET
REG_CMP<5> 2 3 FB4 MC8 STD   21 I/O (b) RESET
REG_CMP<2> 2 3 FB4 MC11 STD   22 I/O I RESET
REG_CMP<14> 2 3 FB4 MC14 STD   23 I/O I RESET
REG_CMP<13> 2 3 FB4 MC15 STD   27 I/O (b) RESET
REG_CMP<11> 2 3 FB4 MC17 STD   28 I/O I RESET
UC_CLK 1 1 FB2 MC2 STD FAST 29 I/O O RESET
CNT_2<0> 17 18 FB2 MC5 STD   30 I/O I RESET
TST_LED 1 7 FB2 MC8 STD FAST 32 I/O O RESET
OUT_CNT_2 18 18 FB2 MC15 STD   37 I/O (b) RESET
FIFO_CLK 5 7 FB1 MC2 STD FAST 39 I/O O  
REG_DIV<2> 2 3 FB1 MC5 STD   40 I/O I RESET
ADC_CLK 5 7 FB1 MC6 STD FAST 41 I/O O  
REG_KEY<0> 3 4 FB1 MC8 STD   42 I/O (b) RESET
REG_KEY<7> 4 5 FB1 MC9 STD   43 I/O/GCK1 GCK/I RESET
REG_KEY<5> 4 5 FB1 MC11 STD   44 I/O/GCK2 GCK RESET
CNT_1<6> 1 6 FB1 MC1 STD     (b) (b) T     RESET
CNT_1<5> 1 5 FB1 MC3 STD     (b) (b) T     RESET
CNT_1<4> 1 4 FB1 MC4 STD     (b) (b) T     RESET
REG_DIV<1> 2 3 FB1 MC7 STD     (b) (b) D     RESET
REG_KEY<6> 4 5 FB1 MC10 STD     (b) (b) D     RESET
REG_KEY<4> 4 5 FB1 MC12 STD     (b) (b) D     RESET
REG_KEY<3> 4 5 FB1 MC13 STD     (b) (b) D     RESET
REG_KEY<1> 4 5 FB1 MC16 STD     (b) (b) D     RESET
OUT_TMP 9 11 FB1 MC18 STD     (b) (b) D     RESET
CNT_1<2> 1 2 FB2 MC3 STD     (b) (b) T     RESET
CNT_1<0> 0 0 FB2 MC4 STD     (b) (b) T     RESET
CNT_1<3> 1 3 FB2 MC7 STD     (b) (b) T     RESET
$OpTx$BUF_OUT_CNT_2_INV$424 17 17 FB2 MC10 STD     (b) (b)        
CNT_2<13> 26 25 FB2 MC18 STD     (b) (b) D     RESET
$OpTx$INV$34 16 16 FB3 MC1 STD     (b) (b)        
REG_CMP<10> 2 3 FB3 MC3 STD     (b) (b) D     RESET
CNT_2<9> 3 12 FB3 MC4 STD     (b) (b) T     RESET
CNT_2<7> 3 10 FB3 MC6 STD     (b) (b) T     RESET
CNT_2<6> 3 9 FB3 MC7 STD     (b) (b) T     RESET
CNT_2<3> 3 6 FB3 MC10 STD     (b) (b) T     RESET
CNT_2<1> 3 4 FB3 MC12 STD     (b) (b) D     RESET
CNT_2<15> 3 18 FB3 MC13 STD     (b) (b) T     RESET
REG_DIV<0> 2 3 FB4 MC3 STD     (b) (b) D     RESET
REG_CMP<9> 2 3 FB4 MC4 STD     (b) (b) D     RESET
REG_CMP<7> 2 3 FB4 MC6 STD     (b) (b) D     RESET
REG_CMP<6> 2 3 FB4 MC7 STD     (b) (b) D     RESET
REG_CMP<4> 2 3 FB4 MC9 STD     (b) (b) D     RESET
REG_CMP<3> 2 3 FB4 MC10 STD     (b) (b) D     RESET
REG_CMP<1> 2 3 FB4 MC12 STD     (b) (b) D     RESET
REG_CMP<15> 2 3 FB4 MC13 STD     (b) (b) D     RESET
REG_CMP<12> 2 3 FB4 MC16 STD     (b) (b) D     RESET
REG_CMP<0> 2 3 FB4 MC18 STD     (b) (b) D     RESET