| Design Name | controller |
| Fitting Status | Successful |
| Software Version | M.63c |
| Device Used | XC9572XL-10-VQ44 |
| Date | 8-14-2011, 9:25PM |
| Macrocells Used | Pterms Used | Registers Used | Pins Used | Function Block Inputs Used |
|---|---|---|---|---|
| 61/72 (85%) | 242/360 (68%) | 55/72 (77%) | 18/34 (53%) | 111/216 (52%) |
|
|
| Signal mapped onto global clock net (GCK1) | CLK |
| Signal mapped onto global clock net (GCK2) | SER_CLK |
| Macrocells in high performance mode (MCHP) | 61 |
| Macrocells in low power mode (MCLP) | 0 |
| Total macrocells used (MC) | 61 |