sc_con Project Status (08/14/2011 - 21:25:24)
Project File:	Scope_Controller.xise	Parser Errors:	No Errors
Module Name:	controller	Implementation State:	Fitted
Target Device:	xc9572xl-10VQ44	Errors:	No Errors
Product Version:	ISE 12.2	Warnings:	No Warnings
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:	System Settings	Final Timing Score:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Âñ 14. àâã 21:24:41 2011	0	0	0
Translation Report	Current	Âñ 14. àâã 21:25:04 2011	0	0	0
CPLD Fitter Report (Text)	Current	Âñ 14. àâã 21:25:11 2011	0	1 Warning (1 new)	0
Power Report

 

Secondary Reports			[-]
Report Name	Status	Generated
Post-Fit Simulation Model Report

Date Generated: 08/14/2011 - 21:26:24