;****************************************************************
;							ШИМ от АЦП
;****************************************************************
.INCLUDE "tn13DEF.INC"
.list

.def tmp=r16
.def tmp0=r17
.def cnt=r19
.def leds=r20
.def ledss=r21

.DSEG

no_data:	.byte 1
ind_n:		.byte 1
led_n:		.byte 1
ckeyh:		.byte 1
nmenu:		.byte 1

.cseg
.org $0a

RESET:
	ldi tmp,low(RAMEND)
	out spl,tmp


	.macro   OUTI
		LDI   R16,@1
		OUT   @0,R16
	.endm
	OUTI   ADCSRA,(1<<ADEN)|(1<<ADIE)|(0<<ADPS2)|(1<<ADPS0) ;Включаем АЦП, его прерывание, настраиваем предделитель тактовой частоты
	OUTI ADCSRB,0 ;источник автосрабатывания отключен
	OUTI   ADMUX,(1<<ADLAR)|(1<<MUX1) ;выравнивание влево (ADCH - 8 старших бит), 
;	OUTI   tccr0a,(1<<com0a1)|(0<<COM0A0)|(1<<wgm01)|(1<<wgm00);НАСТРОЙКА ШИМ
	ldi tmp,$20
	out mcucr,tmp
	ldi tmp,(1<<toie0)
	out timsk0,tmp
	ldi tmp,$01	;преддилитель 64
	out tccr0b,tmp


ldi tmp,0b00000000
out ddrb,tmp

	sei
main:
	sleep
	sleep
	sleep
	sleep

	SBI   ADCSRA,ADSC	;опрашиваем АЦП
	ldi tmp,10
noop:
	subi tmp,1
	brne noop			;ждем ответа АЦП
	
	clr ledss
	clr tmp0
	ldi tmp,20
	cp cnt,tmp
	brsh delenie
led_off:
	clr tmp
	out portb,tmp
	out ddrb,tmp
rjmp main

delenie:
	ldi tmp0,20
delenie_1:
	sub cnt,tmp0
	inc ledss
	cp cnt,tmp
	brsh delenie_1
;	sts led_n,leds
	mov leds,ledss

rjmp main



			tim0_ovf:
				push tmp
				push tmp0
				in tmp0,sreg
				push tmp0
			
				ldi tmp,1
				lds tmp0,ind_n
				cp tmp0,tmp
				breq ind_2

				ldi tmp,2
				cp tmp0,tmp
				brne aaa
				rjmp ind_3				
			aaa:
				ldi tmp,3
				cp tmp0,tmp
				brne ind_1
				rjmp ind_4
			ind_1:
				ldi tmp,1
				sts ind_n,tmp

				ldi tmp,1
;				lds tmp0,led_n
				cp leds,tmp
				breq ind_1_1
				ldi tmp,2
				cp leds,tmp
				breq ind_1_2
				ldi tmp,3
				cp leds,tmp
				brsh ind_1_3
				rjmp exit_led

				ind_1_1:
					ldi tmp,0b00000000
					out portb,tmp
					ldi tmp,0b00000011
					out ddrb,tmp
					ldi tmp,0b00000001
					out portb,tmp
					rjmp exit_led
				ind_1_2:
					ldi tmp,0b00000000
					out portb,tmp
					ldi tmp,0b00000111
					out ddrb,tmp
					ldi tmp,0b00000001
					out portb,tmp
					rjmp exit_led
				ind_1_3:
					ldi tmp,0b00000000
					out portb,tmp
					ldi tmp,0b00001111
					out ddrb,tmp
					ldi tmp,0b00000001
					out portb,tmp
					rjmp exit_led
				
			ind_2:
				ldi tmp,2
				sts ind_n,tmp

				ldi tmp,4
;				lds tmp0,led_n
				cp leds,tmp
				breq ind_2_1
				ldi tmp,5
				cp leds,tmp
				breq ind_2_2
				ldi tmp,6
				cp leds,tmp
				brsh ind_2_3
				rjmp exit_led

				ind_2_1:
					ldi tmp,0b00000000
					out portb,tmp
					ldi tmp,0b00000011
					out ddrb,tmp
					ldi tmp,0b00000010
					out portb,tmp
					rjmp exit_led
				ind_2_2:
					ldi tmp,0b00000000
					out portb,tmp
					ldi tmp,0b00000111
					out ddrb,tmp
					ldi tmp,0b00000010
					out portb,tmp
					rjmp exit_led
				ind_2_3:
					ldi tmp,0b00000000
					out portb,tmp
					ldi tmp,0b00001111
					out ddrb,tmp
					ldi tmp,0b00000010
					out portb,tmp
					rjmp exit_led
			ind_3:
				ldi tmp,3
				sts ind_n,tmp

				ldi tmp,7
;				lds tmp0,led_n
				cp leds,tmp
				breq ind_3_1
				ldi tmp,8
				cp leds,tmp
				breq ind_3_2
				ldi tmp,9
				cp leds,tmp
				brsh ind_3_3
				rjmp exit_led

				ind_3_1:
					ldi tmp,0b00000000
					out portb,tmp
					ldi tmp,0b00000101
					out ddrb,tmp
					ldi tmp,0b00000100
					out portb,tmp
					rjmp exit_led
				ind_3_2:
					ldi tmp,0b00000000
					out portb,tmp
					ldi tmp,0b00000111
					out ddrb,tmp
					ldi tmp,0b00000100
					out portb,tmp
					rjmp exit_led
				ind_3_3:
					ldi tmp,0b00000000
					out portb,tmp
					ldi tmp,0b00001111
					out ddrb,tmp
					ldi tmp,0b00000100
					out portb,tmp
					rjmp exit_led
			ind_4:
				clr tmp
				sts ind_n,tmp

				ldi tmp,10
;				lds tmp0,led_n
				cp leds,tmp
				breq ind_4_1
				ldi tmp,11
				cp leds,tmp
				breq ind_4_2
				ldi tmp,12
				cp leds,tmp
				brsh ind_4_3
				rjmp exit_led

				ind_4_1:
					ldi tmp,0b00000000
					out portb,tmp
					ldi tmp,0b00001001
					out ddrb,tmp
					ldi tmp,0b00001000
					out portb,tmp
					rjmp exit_led
				ind_4_2:
					ldi tmp,0b00000000
					out portb,tmp
					ldi tmp,0b00001011
					out ddrb,tmp
					ldi tmp,0b00001000
					out portb,tmp
					rjmp exit_led
				ind_4_3:
					ldi tmp,0b00000000
					out portb,tmp
					ldi tmp,0b00001111
					out ddrb,tmp
					ldi tmp,0b00001000
					out portb,tmp
					rjmp exit_led
			exit_led:
				pop tmp0
				out sreg,tmp0
				pop tmp0
				pop tmp
				reti





			adc_inc:		;мы тут если сработала SBI ADCSRA,ADSC
				IN cnt,ADCH	;запихиваем значение АЦП в регистр 
				reti
delay_100ms:
;			rcall delay_100ms_2
;			rcall delay_100ms_2
;			rcall delay_100ms_2
;			rcall delay_100ms_2
;			rcall delay_100ms_2
;			rcall delay_100ms_2
;			rcall delay_100ms_2
;			rcall delay_100ms_2
;			rcall delay_100ms_2
;			rcall delay_100ms_2
;			ret
;		delay_100ms_2:
	ldi tmp0,$a0
	rjmp delay_ms1
delay_10ms:
	ldi tmp0,$10
	rjmp delay_ms1
delay_ms:
	ldi tmp,0
delay_ms1:
	rcall delay_us
	rcall delay_us
	rcall delay_us
	rcall delay_us
	subi tmp0,1
	brne delay_ms
	ret

delay_us:
	subi tmp,1
	nop
	brne delay_us
	ret




;		Address Labels Code Comments
.org $00
rjmp RESET ; Reset Handler
reti	;rjmp EXT_INT0 ; IRQ0 Handler
	reti	;rjmp PCINT0 ; PCINT0 Handler
rjmp tim0_ovf ; Timer0 Overflow Handler
	reti	;rjmp EE_RDY ; EEPROM Ready Handler
	reti	;rjmp ANA_COMP ; Analog Comparator Handler
	reti	;rjmp TIM0_COMPA ; Timer0 CompareA Handler
	reti	;rjmp TIM0_COMPB ; Timer0 CompareB Handler
	reti	;rjmp WATCHDOG ; Watchdog Interrupt Handler
rjmp ADC_inc ; ADC Conversion Handler

.exit