/*******************************************************************************
// Wait until I2C flag cleared
// input:
//   I2C_Flag - I2C flag (one of I2C_F_XXX values)
// return:
//   SUCCESS if flag cleared or ERROR in case of timeout
*******************************************************************************/
ErrorStatus wait_flag_reset (volatile u16 *reg, u16 Flag)
{
  u32 timer;
 
  timer_reset (&timer);
   while (timer_active (&timer, 3)) // Wait until flag cleared
  {
      if (!(*reg & Flag)) return SUCCESS;
   }
   return ERROR;
}

ErrorStatus i2c_init (void)
{
  const u32 i2c_APB_freq = 36;  // частота шины APB 32МГц
  const u32 i2c_freq = 400; // частота i2c= 400 кГц
  // CCR = 45, это кол-во тактов APB1 на полупериод SCL (36МГц/(400КГц * 2))
//  u32 i2c_ccr = 180;  // 36MHz / (2 * 100kHz) = 180
  const u32 i2c_ccr = (i2c_APB_freq * 1000) / (2 * i2c_freq);  // i2c_APB_freq / (2 * 400kHz) = 45
  // TRISE = 9, это кол-во тактов APB1, через которое проверяется состояние SCL
  // при переходе в откл. состояние (из 0 в 1),
  // это время должно быть чуть больше 1 мкс (1мкс/(1/i2c_APB_freq)+1) = i2c_APB_freq + 1
  const u32 t_rise = i2c_APB_freq + 1;
 
//---------- из Errata------------------------------------//
//1.Disable the I2C peripheral by clearing the PE bit in I2Cx_CR1 register.
   I2C1->CR1 &= ~I2C_CR1_PE;
//2. Configure the SCL and SDA I/Os as General Purpose Output Open-Drain, High level (Write 1 to GPIOx_ODR).
  GPIOB->CRL = GPIO_CRL_MODE0_INPUT     | GPIO_CRL_CNF0_IN_FL
            | GPIO_CRL_MODE1_INPUT      | GPIO_CRL_CNF1_IN_FL
            | GPIO_CRL_MODE2_INPUT      | GPIO_CRL_CNF2_IN_FL
            | GPIO_CRL_MODE3_INPUT      | GPIO_CRL_CNF3_IN_FL
            | GPIO_CRL_MODE4_INPUT      | GPIO_CRL_CNF4_IN_FL
            | GPIO_CRL_MODE5_INPUT      | GPIO_CRL_CNF5_IN_FL
            | GPIO_CRL_MODE6_OUTPUT10M  | GPIO_CRL_CNF6_OUT_GP_PP
            | GPIO_CRL_MODE7_OUTPUT10M  | GPIO_CRL_CNF7_OUT_GP_PP;
  GPIOB->BSRR = GPIO_BSRR_BS6 | GPIO_BSRR_BS7;
//3. Check SCL and SDA High level in GPIOx_IDR.
  wait_flag_set ((u16 *)GPIOB->IDR, GPIO_IDR_IDR6 | GPIO_IDR_IDR7);
//  while (!(GPIOB->IDR &(GPIO_IDR_IDR6 | GPIO_IDR_IDR7)));
//4. Configure the SDA I/O as General Purpose Output Open-Drain, Low level (Write 0 to GPIOx_ODR).
  GPIOB->CRL = GPIO_CRL_MODE0_INPUT     | GPIO_CRL_CNF0_IN_FL
            | GPIO_CRL_MODE1_INPUT      | GPIO_CRL_CNF1_IN_FL
            | GPIO_CRL_MODE2_INPUT      | GPIO_CRL_CNF2_IN_FL
            | GPIO_CRL_MODE3_INPUT      | GPIO_CRL_CNF3_IN_FL
            | GPIO_CRL_MODE4_INPUT      | GPIO_CRL_CNF4_IN_FL
            | GPIO_CRL_MODE5_INPUT      | GPIO_CRL_CNF5_IN_FL
            | GPIO_CRL_MODE6_OUTPUT10M  | GPIO_CRL_CNF6_OUT_GP_PP
            | GPIO_CRL_MODE7_OUTPUT10M  | GPIO_CRL_CNF7_OUT_GP_OD;
  GPIOB->BRR = GPIO_BRR_BR7;
//5. Check SDA Low level in GPIOx_IDR.
  wait_flag_reset ((u16 *)GPIOB->IDR, GPIO_IDR_IDR7);
//  while (GPIOB->IDR & GPIO_IDR_IDR7);
//6. Configure the SCL I/O as General Purpose Output Open-Drain, Low level (Write 0 to GPIOx_ODR).
  GPIOB->CRL = GPIO_CRL_MODE0_INPUT     | GPIO_CRL_CNF0_IN_FL
            | GPIO_CRL_MODE1_INPUT      | GPIO_CRL_CNF1_IN_FL
            | GPIO_CRL_MODE2_INPUT      | GPIO_CRL_CNF2_IN_FL
            | GPIO_CRL_MODE3_INPUT      | GPIO_CRL_CNF3_IN_FL
            | GPIO_CRL_MODE4_INPUT      | GPIO_CRL_CNF4_IN_FL
            | GPIO_CRL_MODE5_INPUT      | GPIO_CRL_CNF5_IN_FL
            | GPIO_CRL_MODE6_OUTPUT10M  | GPIO_CRL_CNF6_OUT_GP_OD
            | GPIO_CRL_MODE7_OUTPUT10M  | GPIO_CRL_CNF7_OUT_GP_OD;
  GPIOB->BRR = GPIO_BRR_BR6;
//7. Check SCL Low level in GPIOx_IDR.
  wait_flag_reset ((u16 *)GPIOB->IDR, GPIO_IDR_IDR6);
//  while (GPIOB->IDR & GPIO_IDR_IDR6);
//8. Configure the SCL I/O as General Purpose Output Open-Drain, High level (Write 1 to GPIOx_ODR).
  GPIOB->BSRR = GPIO_BSRR_BS6;
//9. Check SCL High level in GPIOx_IDR.
  wait_flag_set ((u16 *)GPIOB->IDR, GPIO_IDR_IDR6);
//  while (!(GPIOB->IDR & GPIO_IDR_IDR6));
//10. Configure the SDA I/O as General Purpose Output Open-Drain , High level (Write 1 to GPIOx_ODR).
  GPIOB->BSRR = GPIO_BSRR_BS7;
//11. Check SDA High level in GPIOx_IDR.
  wait_flag_set ((u16 *)GPIOB->IDR, GPIO_IDR_IDR7);
//  while (!(GPIOB->IDR & GPIO_IDR_IDR7));
//12. Configure the SCL and SDA I/Os as Alternate function Open-Drain.
  GPIOB->CRL = GPIO_CRL_MODE0_INPUT     | GPIO_CRL_CNF0_IN_FL
            | GPIO_CRL_MODE1_INPUT      | GPIO_CRL_CNF1_IN_FL
            | GPIO_CRL_MODE2_INPUT      | GPIO_CRL_CNF2_IN_FL
            | GPIO_CRL_MODE3_INPUT      | GPIO_CRL_CNF3_IN_FL
            | GPIO_CRL_MODE4_INPUT      | GPIO_CRL_CNF4_IN_FL
            | GPIO_CRL_MODE5_INPUT      | GPIO_CRL_CNF5_IN_FL
            | GPIO_CRL_MODE6_OUTPUT10M  | GPIO_CRL_CNF6_OUT_AF_OD
            | GPIO_CRL_MODE7_OUTPUT10M  | GPIO_CRL_CNF7_OUT_AF_OD;
//13. Set SWRST bit in I2Cx_CR1 register.
  I2C1->CR1 = I2C_CR1_SWRST;
//14. Clear SWRST bit in I2Cx_CR1 register.
  I2C1->CR1 = 0;
//15. Enable the I2C peripheral by setting the PE bit in I2Cx_CR1 register.
//----------//
  I2C1->CR2 = (I2C_CR2_FREQ & (i2c_APB_freq / 2)) // Peripheral Clock Frequency in MHz */
        | I2C_CR2_ITERREN   * 0   // Error Interrupt Enable
        | I2C_CR2_ITEVTEN   * 0   // Event Interrupt Enable
        | I2C_CR2_ITBUFEN   * 0   // Buffer Interrupt Enable
        | I2C_CR2_DMAEN     * 0   // DMA Requests Enable
        | I2C_CR2_LAST      * 0;  // DMA Last Transfer
 
  I2C1->TRISE = t_rise;
 
  I2C1->CCR = (I2C_CCR_CCR & i2c_ccr)
        | I2C_CCR_FS_F;   // Fm mode 400 kHz
  // Set I2C own address: 0x00, 7-bit
   I2C1->OAR1 = (1 << 14); // Bit 14 should be kept as 1
 
  I2C1->CR1 = I2C_CR1_PE    * 1   // Peripheral Enable
        | I2C_CR1_SMBUS     * 0   // SMBus Mode
        | I2C_CR1_SMBTYPE   * 0   // SMBus Type
        | I2C_CR1_ENARP     * 0   // ARP Enable
        | I2C_CR1_ENPEC     * 0   // PEC Enable
        | I2C_CR1_ENGC      * 0   // General Call Enable
        | I2C_CR1_NOSTRETCH * 0   // Clock Stretching Disable (Slave mode)
        | I2C_CR1_START     * 0   // Start Generation
        | I2C_CR1_STOP      * 0   // Stop Generation
        | I2C_CR1_ACK       * 1   // Acknowledge Enable
        | I2C_CR1_POS       * 0   // Acknowledge/PEC Position (for data reception)
        | I2C_CR1_PEC       * 0   // Packet Error Checking
        | I2C_CR1_ALERT     * 0   // SMBus Alert
        | I2C_CR1_SWRST     * 0;  // Software Reset

   // Wait until I2C bus is free
  ErrorStatus stat;
  stat = wait_flag_reset (&I2C1->SR2, I2C_SR2_BUSY);
  return stat;
}

ErrorStatus i2c_write (u8 addr, u8 *cmd, u16 len, u8 cont)
{
  I2C1->CR1 |= I2C_CR1_START;//стартуем
  if (wait_flag_set (&I2C1->SR1, I2C_SR1_SB) == ERROR) return ERROR;  // Wait for EV5

  I2C1->DR = addr & ~0x01; //передаем адрес устройства, бит 0 = 0 (запись)
  if (wait_flag_set (&I2C1->SR1, I2C_SR1_ADDR) == ERROR) return ERROR;  // Wait for EV6
  if (I2C1->SR1 & I2C_SR1_AF) return ERROR;  // if NACK
  (void) I2C1->SR1;  // clear ADDR
  (void) I2C1->SR2;  // clear ADDR

   I2C1->DR = *cmd++;  // Send first byte (EV8)
   while (--len)       // Send rest of data (if present)
  {
      if (wait_flag_set (&I2C1->SR1, I2C_SR1_TXE) == ERROR) return ERROR; // Wait for BTF flag set
      I2C1->DR = *cmd++;// Transmit byte via I2C
   }
   if (wait_flag_set (&I2C1->SR1, I2C_SR1_TXE | I2C_SR1_BTF) == ERROR) return ERROR; // Wait for BTF flag set

  if (!cont)
  {
    I2C1->CR1 |= I2C_CR1_STOP;
    if (wait_flag_reset (&I2C1->SR1, I2C_SR1_STOPF) == ERROR) return ERROR;
  }
  return SUCCESS;
}


ErrorStatus i2c_read (u8 addr, u8 *data, u16 len)
{
   I2C1->CR1 |= I2C_CR1_START; //рестарт!!!
   if (wait_flag_set (&I2C1->SR1, I2C_SR1_SB) == ERROR) return ERROR;  // Wait for EV5

   //передаем адрес устройства, но теперь для чтения
   I2C1->DR = addr | 0x01;
   if (wait_flag_set (&I2C1->SR1, I2C_SR1_ADDR) == ERROR) return ERROR; // Wait for EV6
 
   // There are can be three cases:
   //   read 1 byte
   //   read 2 bytes
   //   read more than 2 bytes
   if (len == 1) // Receive 1 byte (AN2824 figure 2)
  {
      I2C1->CR1 &= ~I2C_CR1_ACK;  // Disable I2C acknowledgment   
      __disable_irq();            // EV6_1 must be atomic operation (AN2824)
      (void) I2C1->SR1;           // Clear ADDR bit
      (void) I2C1->SR2;
      I2C1->CR1 |= I2C_CR1_STOP;  // Generate a STOP condition
      __enable_irq();
      // Wait for RxNE flag (receive buffer not empty) EV7
      if (wait_flag_set (&I2C1->SR1, I2C_SR1_RXNE) == ERROR) return ERROR;
      *data = (u8)I2C1->DR;       // Read received byte
   }
  else if (len == 2) // Receive 2 bytes (AN2824 figure 2)
  {
      I2C1->CR1 |= I2C_CR1_POS;   // Set POS flag (NACK position next)
      __disable_irq();            // EV6_1 must be atomic operation (AN2824)
    (void) I2C1->SR1;
      (void) I2C1->SR2;           // Clear ADDR bit
      I2C1->CR1 &= ~I2C_CR1_ACK;  // Disable I2C acknowledgment
      __enable_irq();
      // Wait for BTF flag set (byte transfer finished) EV7_3
      if (wait_flag_set (&I2C1->SR1, I2C_SR1_BTF) == ERROR) return ERROR;
      __disable_irq();            // This should be atomic operation
      I2C1->CR1 |= I2C_CR1_STOP;  // Generate a STOP condition
      *data++ = (u8)I2C1->DR;     // Read first received byte
      __enable_irq();
      *data = (u8)I2C1->DR;       // Read second received byte
   I2C1->CR1 &= ~I2C_CR1_POS;   // Clear POS flag // NACK position current
   }
  else // Receive more than 2 bytes (AN2824 figure 1)
  {
    (void) I2C1->SR1;
      (void) I2C1->SR2;           // Clear ADDR bit
      while (len-- > 2)          // Read received bytes into buffer
    {
         // Wait for BTF (cannot guarantee 1 transfer completion time)
         if (wait_flag_set (&I2C1->SR1, I2C_SR1_BTF) == ERROR) return ERROR;
         *data++ = (u8)I2C1->DR;
      }
      // Wait for BTF flag set (byte transfer finished) EV7_2
      if (wait_flag_set (&I2C1->SR1, I2C_SR1_BTF) == ERROR) return ERROR;
      I2C1->CR1 &= ~I2C_CR1_ACK;  // Disable the I2C acknowledgment
      __disable_irq();
      I2C1->CR1 |= I2C_CR1_STOP;  // Generate a STOP condition
      *data++ = (u8)I2C1->DR;     // Read received byte N-1
      __enable_irq();
      // Wait for last byte received
     if (wait_flag_set (&I2C1->SR1, I2C_SR1_RXNE) == ERROR) return ERROR;
      *data = (u8)I2C1->DR;// Read last received byte
   }
   // Wait for a STOP flag
   if (wait_flag_reset (&I2C1->SR1, I2C_SR1_STOPF) == ERROR) return ERROR;
  I2C1->CR1 |= I2C_CR1_ACK;   // Enable Acknowledgment
 
   return SUCCESS;   
}


ErrorStatus i2c_read16 (u8 addr, u16 *data, u16 len)
{
  u16 first_byte;
  u16 second_byte;
 
   I2C1->CR1 |= I2C_CR1_START; //рестарт!!!
   if (wait_flag_set (&I2C1->SR1, I2C_SR1_SB) == ERROR) return ERROR; // Wait for EV5
   //передаем адрес устройства, но теперь для чтения
   I2C1->DR = addr | 0x01;
   if (wait_flag_set (&I2C1->SR1, I2C_SR1_ADDR) == ERROR) return ERROR; // Wait for EV6
 
  if (len == 1) // Receive only 2 bytes (AN2824 figure 2)
  {
    I2C1->CR1 |= I2C_CR1_POS;       // Set POS flag (NACK position next)
    __disable_irq();                // This should be atomic operation
    (void) I2C1->SR1;               
    (void) I2C1->SR2;               // reset ADDR
    I2C1->CR1 &= ~I2C_CR1_ACK;      // NACK, Disable the I2C acknowledgment
    __enable_irq();
    // Wait for BTF flag set (byte transfer finished) EV7_3
    if (wait_flag_set (&I2C1->SR1, I2C_SR1_BTF) == ERROR) return ERROR;
    __disable_irq();                // This should be atomic operation
    I2C1->CR1 |= I2C_CR1_STOP;      // Generate a STOP condition
    first_byte = I2C1->DR << 8;  // Read received byte N-1
    __enable_irq();
    second_byte = I2C1->DR;      // Read second received byte
    *data = (first_byte << 8) | second_byte;
    // Wait for a STOP flag
    if (wait_flag_reset (&I2C1->SR1, I2C_SR1_STOPF) == ERROR) return ERROR;
    I2C1->CR1 &= ~I2C_CR1_POS;  // Clear POS flag // NACK position current
  }
  else
  {
    (void) I2C1->SR1;                       
    (void) I2C1->SR2;                       // reset ADDR
    while (--len)
    {
      if (wait_flag_set (&I2C1->SR1, I2C_SR1_RXNE) == ERROR) return ERROR;
      first_byte = I2C1->DR;
      if (wait_flag_set (&I2C1->SR1, I2C_SR1_RXNE) == ERROR) return ERROR;
      second_byte = I2C1->DR;
      *data++ = (first_byte << 8) | second_byte;
    }
    // receive last two bytes
    if (wait_flag_set (&I2C1->SR1, I2C_SR1_RXNE) == ERROR) return ERROR;   
    I2C1->CR1 &= ~I2C_CR1_ACK;      // NACK, Disable the I2C acknowledgment
    __disable_irq();                // This should be atomic operation
    I2C1->CR1 |= I2C_CR1_STOP;      // Generate a STOP condition
    first_byte = I2C1->DR;          // Read received byte N-1
    __enable_irq();
   
    if (wait_flag_set (&I2C1->SR1, I2C_SR1_RXNE) == ERROR) return ERROR;
    second_byte = I2C1->DR;      // Read second received byte
    // Wait for a STOP flag
    if (wait_flag_reset (&I2C1->SR1, I2C_SR1_STOPF) == ERROR) return ERROR;
    *data = (first_byte << 8) | second_byte;
  }
  I2C1->CR1 |= I2C_CR1_ACK;   // Enable Acknowledgment
   return SUCCESS;   
}