RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN;

    GPIOA->MODER = (GPIOA->MODER & ~(GPIO_MODER_MODE6)) | GPIO_MODER_MODE6_1;
    GPIOA->OTYPER &= ~GPIO_OTYPER_OT6;
    GPIOA->OSPEEDR |= GPIO_OSPEEDR_OSPEED6;
    GPIOA->PUPDR &= ~GPIO_PUPDR_PUPD6;
    GPIOA->AFR[0] = (GPIOA->AFR[0] & ~(GPIO_AFRL_AFSEL6)) | (GPIO_AFRL_AFSEL6_3 | GPIO_AFRL_AFSEL6_2 | GPIO_AFRL_AFSEL6_1);

    RCC->APB2ENR |= RCC_APB2ENR_TIM16EN;
    RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN;

    uint16_t data[] = { 2400, 600, 600, 600, 1200, 600 };

    DMA1_Channel3->CPAR = (uint32_t)&TIM16->CCR1;
    DMA1_Channel3->CMAR = (uint32_t)&data[0];
    DMA1_Channel3->CNDTR = 6;
    DMA1_Channel3->CCR &= ~(DMA_CCR_MSIZE | DMA_CCR_PSIZE | DMA_CCR_PINC | DMA_CCR_CIRC);
    DMA1_Channel3->CCR |= DMA_CCR_PL | DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0 | DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE;
    DMA1_Channel3->CCR |= DMA_CCR_EN;

    TIM16->PSC = 35;
    TIM16->ARR = 60000;
    TIM16->CCR1 = 100;
    TIM16->CCMR1 = (TIM16->CCMR1 & ~(TIM_CCMR1_OC1M | TIM_CCMR1_OC1PE | TIM_CCMR1_CC1S)) | (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0);
    TIM16->CCER = (TIM16->CCER & ~TIM_CCER_CC1P) | TIM_CCER_CC1E;
    TIM16->BDTR |= TIM_BDTR_MOE;
    TIM16->DIER |= TIM_DIER_CC1DE;

    TIM16->CR1 |= TIM_CR1_CEN;

    NVIC_SetPriority(DMA1_Channel3_IRQn, 0);
    NVIC_EnableIRQ(DMA1_Channel3_IRQn);

DMA1_CSELR->CSELR = (DMA1_CSELR->CSELR & ~DMA_CSELR_C3S) | (0x04 << DMA_CSELR_C3S_Pos);