Features
We believe our simulation models are the most accurate and the most complete on the market today. A
summary of model capabilities is listed below:
• Supports the entire instruction set.
• Supports all port and other I/O pin operations.
• Supports all counter/timers including seperate prescalers, capture compare and PWM modes.
• Supports watchdog timer.
• Supports serial U(S)ART.
• Supports master slave SPI, USI and TWI serial interfaces.
• Supports Analogue-to-Digital Conversion (ADC) and analogue comparator modules in all modes.
• Supports all internal and external interrupt modes.
• Supports internal code and data EEPROM memory inc. code protection and data persistence.
• Internally generated processor clock for performance. Event timing accurate to one clock period.
• Provides internal consistency checks on code (e.g. execution of invalid op-codes, illegal memory accesses,
stack overflow checking, etc.).
• Fully integrated in to the VSM source level debugging system.
• Fully integrated into the Proteus Diagnostic Control System.
Limitations
The following is a listing of known limitations in the current version of the AVR® family:
x Brown-out Reset is not implemented.
x Power supply voltage changing is not supported.
x JTAG and other in-circuit debugging interfaces are not supported.
x External programming of memories is not supported.
x Electrical characteristics dependency of the temperature is not implemented.