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Код: Выделить всё

.def temp=R16
.def tembr=R17
.def tembr2=R18
.cseg
rjmp RESET ; Reset Handler
rjmp EXT_INT0 ; IRQ0 Handler
rjmp EXT_INT1 ; IRQ1 Handler
rjmp TIM2_COMP ; Timer2 Compare Handler
rjmp TIM2_OVF ; Timer2 Overflow Handler
rjmp TIM1_CAPT ; Timer1 Capture Handler
rjmp TIM1_COMPA ; Timer1 CompareA Handler
rjmp TIM1_COMPB ; Timer1 CompareB Handler
rjmp TIM1_OVF ; Timer1 Overflow Handler
rjmp TIM0_OVF ; Timer0 Overflow Handler
rjmp SPI_STC ; SPI Transfer Complete Handler
rjmp USART_RXC ; USART RX Complete Handler
rjmp USART_UDRE ; UDR Empty Handler
rjmp USART_TXC ; USART TX Complete Handler
rjmp ADCC ; ADC Conversion Complete Handler
rjmp EE_RDY ; EEPROM Ready Handler
rjmp ANA_COMP ; Analog Comparator Handler
rjmp TWSI ; Two-wire Serial Interface
rjmp SPM_RDY

;RESET:
EXT_INT0:
EXT_INT1:
TIM2_COMP:
TIM2_OVF:
TIM1_CAPT:
;TIM1_COMPA:
;TIM1_COMPB:
TIM1_OVF:
TIM0_OVF:
SPI_STC:
USART_RXC:
USART_UDRE:
USART_TXC:
ADCC:
EE_RDY:
ANA_COMP:
TWSI:
SPM_RDY:
reti
Reset:
ldi temp,0b00010000
out DDRC,temp
ldi temp,0b00010000
out TIMSK,temp
ldi temp,0b00000001
out TCCR1B,temp
ldi tembr,0x08
out OCR1AH,temp
ldi temp,1
out OCR1AL,temp
ldi tembr2,0x16
out OCR1BH,temp
ldi temp,1
out OCR1BL,temp
ldi temp,0
out TCNT1H,temp
out TCNT1L,temp

sei
rjmp Loop
TIM1_CompA:
ldi temp,0b00010000
out PortC,temp
ldi temp,0b00001000
out TIMSK,temp
reti
TIM1_CompB:
ldi temp,0
out TCNT1H,temp
out TCNT1L,temp
out PortC,temp
ldi temp,0b00010000
out TIMSK,temp
reti
Loop:
SBIS PINC,1
rjmp left
SBIS PINC,0
rjmp right
rjmp Loop
left:
dec tembr
ldi tembr2,0
add tembr2,tembr
add tembr2,tembr
out OCR1AH,tembr
out OCR1BH,tembr2
rjmp Loop
right:
inc tembr
ldi tembr2,0
add tembr2,tembr
add tembr2,tembr
out OCR1AH,tembr
out OCR1BH,tembr2
rjmp Loop

Код: Выделить всё

.include "tn2313def.inc"	      

.dseg


.cseg
		  ldi R16,low(RamEnd)  ;установка указателя стека
          out SPL,R16
		  
		  ldi R16,0b11111111   ;настройка портов B
          out DDRB,R16

		  ldi R16,0b00011111   ;настройка портов D
          out DDRD,R16
	clr r23
	clr r24
	clr r25
	clr r26
		 
Start:
	in r16,PinD		; пересылаем r16
	sbic PinD,4		; бит 4 
	rcall CycleINC
	
Indic:
          ldi R17,0b00000111                       
          out PortD,R17
		  mov R22,r23
		  rcall Decoder
		  sbic PinD,5
		  sbr r17,0b10000000
		  out PortB,R17
		  rcall Delay1         
     
          ldi R17,0b00001011                         
          out PortD,R17
		  mov R22,r24
          rcall Decoder        
          out PortB,R17      
          rcall Delay1 

          ldi R17,0b00001101                          
          out PortD,R17
		  mov R22,r25
          rcall Decoder        
          out PortB,R17      
          rcall Delay1 

		  ldi R17,0b00001110                 
		  out PortD,R17
		  mov R22,r26
          rcall Decoder        
          out PortB,R17    
          rcall Delay1 
		
	in r3,PinD	; пересылаем порт в r3
	and r3,r16	; проверяем, изменился ли 4-й бит
	sbrc r3,4	; бит 4 в r3 очищен?
	rjmp Indic	; нет => Индикация
	rjmp Start 	; да => Старт
	
CycleINC:
	sbic PinD,5
	rjmp CycleDEC
	inc r23
	cpi r23,10
	breq M
	ret
M:
	clr r23	
	inc r24
	cpi r24,10
	breq F
	ret
F:
	clr r24	
	inc r25
	cpi r25,10
	breq W
	ret
W:
	clr r25	
	inc r26
	cpi r26,10
	breq T
	ret
T:
	clr r26
	ret

	 		

CycleDEC:
	dec r23
	cpi r23,255
	breq M1
	ret
M1:
	ldi r23,9
	dec r24
	cpi r24,255
	breq F1
	ret
F1:
	ldi r24,9	
	dec r25
	cpi r25,255
	breq W1
	ret
W1:
	ldi r25,9
	dec r26
	cpi r26,255
	breq T1
	rjmp Indic
T1:
	ldi r26,9
	rjmp Indic
		
Decoder:				

          ldi ZL,Low(DcMatrix*2)   	;инициализация массива
          ldi ZH,High(DcMatrix*2)
		  ldi R18,0 		;прибавление переменной
          add ZL,R22           		;к 0-му адресу массива
          adc ZH,R18

          lpm                     ;загрузка значения
          mov R17,r0  
		  ret

DcMatrix:
;массив - таблица истинности декодера
              ; hgfedcba   hgfedcba
          .db 0b00111111,0b00000110	;0,1
          .db 0b01011011,0b01001111	;2,3
          .db 0b01100110,0b01101101	;4,5
          .db 0b01111101,0b00000111	;6,7
          .db 0b01111111,0b01101111	;8,9
          
Delay1:
           ldi R20,20
           ldi R21,11
d11:       
		   dec R20
           brne d11
           dec R21
           brne d11
           ret