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Код: Выделить всё

;*****************************************************************
;*	file: macros.inc
;*
;*	Description:
;*	Source file for application note AVR001 - Conditional Assembly
;*	and Portability Macros.
;*
;*	Defines a number of macros that makes it easier to access
;*	IO registers and extended IO registers (or SRAM locations up
;*  to adress $FF if applicable).
;*	The macros can be used to produce code that assembles to
;*	any target AVR, without considering if the accessed IO
;*	registers are located in low, standard or extended IO space
;*
;* $Revision: 2.2 $	
;* $Author: jllassen $
;* $Date: Wednesday, January 26, 2005 10:55:18 UTC $
;*****************************************************************

;*********************************************************
;*	BIT access anywhere in IO or lower $FF of data space
;*	SETB - SET Bit in IO of data space
;*	CLRB - CLeaR Bit in IO of data space
;*********************************************************

.MACRO SETB 		;Arguments: Address, Bit, Register
	.if @1>7
		.message "Only values 0-7 allowed for Bit parameter"
	.endif
	.if @0>0x3F
		lds  @2, @0
		sbr  @2, (1<<@1)
		sts  @0, @2
	.elif @0>0x1F
		in   @2, @0
		sbr  @2, (1<<@1)
		out  @0, @2
	.else
		sbi  @0, @1
	.endif
.ENDMACRO

.MACRO CLRB 		;Arguments: Address, Bit, Register
	.if @1>7
		.message "Only values 0-7 allowed for Bit parameter"
	.endif
	.if @0>0x3F
		lds  @2, @0
		cbr  @2, (1<<@1)
		sts  @0, @2
	.elif @0>0x1F
		in   @2, @0
		cbr  @2, (1<<@1)
		out  @0, @2
	.else
		cbi  @0, @1
	.endif
.ENDMACRO

;*********************************************************
;*	Bit test anywhere in IO or in lower $FF of data space
;*  SKBS : SKip if Bit Set
;*  SKBC : SKip if Bit Cleared
;*********************************************************
.MACRO SKBS  		;Arguments: Address, Bit, Register
	.if @1>7
		.message "Only values 0-7 allowed for Bit parameter"
	.endif
	.if @0>0x3F
		lds  @2, @0
		sbrs @2, @1
	.elif @0>0x1F
		in   @2, @0
		sbrs @2, @1
	.else
		sbis @0, @1
	.endif
.ENDMACRO

.MACRO SKBC  		;Arguments: Address, Bit, Register
	.if @1>7
		.message "Only values 0-7 allowed for Bit parameter"
	.endif
	.if @0>0x3F
		lds	 @2, @0
		sbrc @2, @1
	.elif @0>0x1F
		in	 @2, @0
		sbrc @2, @1
	.else
		sbic @0, @1
	.endif
.ENDMACRO

;*********************************************************
;*	Byte access anywhere in IO or lower $FF of data space
;* 	STORE - Store register in IO or data space
;* 	LOAD  - Load register from IO or data space
;*********************************************************

.MACRO STORE 		;Arguments: Address, Register
	.if	@0>0x3F
		sts	@0, @1
	.else
		out	@0, @1
	.endif
.ENDMACRO

.MACRO LOAD 		;Arguments: Register, Address
	.if	@1>0x3F
		lds	@0, @1
	.else
		in	@0, @1
	.endif
.ENDMACRO

Код: Выделить всё

.include "m168def.inc"

.dseg
.cseg
	.ORG 0x000 ; Reset Handler
    rjmp Reset	  
	.ORG 0x001 ; IRQ0 Handler
	RETI  
	.ORG 0x002 ; IRQ1 Handler
	RETI 
	.ORG 0x003 ; PCINT0 Handler
	RETI
	.ORG 0x004 ; PCINT1 Handler
	RETI
	.ORG 0x005 ; PCINT2 Handler
	RETI
	.ORG 0x006 ; Watchdog Timer Handler
	RETI 
	.ORG 0x007 ; Timer2 Compare A Handler
	RETI 
	.ORG 0x008 ; Timer2 Compare B Handler
	RETI 
	.ORG 0x009 ; Timer2 Overflow Handler
	rjmp Klac
	.ORG 0x00A ; Timer1 Capture Handler
	RETI 
	.ORG 0x00B ; Timer1 Compare A Handler
	RETI
	.ORG 0x00C ; Timer1 Compare B Handler
	RETI 
	.ORG 0x00D ; Timer1 Overflow Handler
	RETI
	.ORG 0x00E ; Timer0 Compare A Handler
	RETI 
	.ORG 0x00F ; Timer0 Compare B Handler
	RETI
	.ORG 0x010 ; Timer0 Overflow Handler
	RETI
	.ORG 0x011 ; SPI Transfer Complete Handler
	RETI
	.ORG 0x012 ; USART, RX Complete Handler
	RETI
	.ORG 0x013 ; USART, UDR Empty Handler
	RETI
	.ORG 0x014 ; USART, TX Complete Handler
	RETI
	.ORG 0x015 ; ADC Conversion Complete Handler
	RETI
	.ORG 0x016 ; EEPROM Ready Handler
	RETI
	.ORG 0x017 ; Analog Comparator Handler
	RETI 
	.ORG 0x018 ; 2-wire Serial Interface Handler
	RETI
	.ORG 0x019 ; Store Program Memory Ready Handler
	RETI
	.ORG   INT_VECTORS_SIZE	; Конец таблицы прерываний
	
Reset:

	
	ldi r16,low(RamEnd)
	out SPL,r16

	ldi r16,high(RamEnd)
	out SPH,r16

	ldi r16,0b00001111
	out DDRB,r16

	ldi r16,0b11111111
	out DDRD,r16

	cli ; запрещаем прерывания

	ldi r16,(1<<OCIE2A)|(1<<OCIE2B)|(1<<TOIE2); Запрещаем прерывания TC2, обнуляя OCIE2x и TOIE2 
	sts TIMSK2,r16

	ldi r16,(1<<AS2); Переводим ТС2 в асинхронный режим
	sts ASSR,r16

	rcall Delay1 

	clr r16
	sts TCNT2,r16; Обнуляем ТСNТ2
	
	ldi r16,(1<<CS22)|(1<<CS20); Устанавливаем предделитель = 128
	sts TCCR2B,r16

re:	
	lds r16,ASSR
	andi r16,0b00011111
	brne re ; ждем пока обнулятся биты : TCN2UB, OCR2AUB, OCR2BUB, TCR2AUB и TCR2BUB.
	
	clr r16
	ldi r16,(1<<OCF2A)|(1<<OCF2B)|(1<<TOV2) ; Обнуляем флаги прерываний Timer/Counter2
	sts TIFR2,r16

	ldi r16,(1<<TOIE2);Разрешаем прерывание по переполнению таймера 2
	sts TIMSK2,r16

	sei	


Indic:					 ;Цикл индикации	

	mov R22,R23
	rcall Decoder
	out PortD,R17
	sbi PortB,3
	rcall Delay       
    cbi PortB,3
	 
	
	mov R22,R24
	rcall Decoder
	cbr R17,0b10000000         
	out PortD,R17      
	sbi PortB,2
	rcall Delay
	cbi PortB,2

	mov R22,r25
	rcall Decoder        
	out PortD,R17      
	sbi PortB,1
	rcall Delay 
	cbi PortB,1

	mov R22,r26
	rcall Decoder       
	out PortD,R17    
	sbi PortB,0
	rcall Delay
	cbi PortB,0
	
	rjmp Indic 			

Klac:					; Переходим сюда каждые 128 переподнений Второго таймера
rcall CycleINC
reti

CycleINC:				;!!!ЦИКЛ УВЕЛИЧЕНИЯ!!!	
	inc r23
	cpi r23,7
	breq M
	ret
M:
	clr r23	
	inc r24
	cpi r24,7
	breq F
	ret
F:
	clr r24	
	inc r25
	cpi r25,3
	breq W
	ret
W:
	clr r25	
	inc r26
	cpi r26,2
	breq T
	ret
T:
	clr r26
	reti


Decoder:				

	ldi ZL,Low(DcMatrix*2)   	;инициализация массива
	ldi ZH,High(DcMatrix*2)
	ldi R18,0 					;прибавление переменной
	add ZL,R22           		;к 0-му адресу массива
	adc ZH,R18

	lpm                     	;загрузка значения
    mov R17,r0  
	ret


DcMatrix:
;массив - таблица истинности декодера
        ; hgfedcba   hgfedcba
	.db 0b11000000,0b11111001	;0,1
	.db 0b10100100,0b10110000	;2,3
	.db 0b10011001,0b10010010	;4,5
	.db 0b10000010,0b11111000	;6,7
	.db 0b10000000,0b10010000	;8,9


	Delay:
	ldi R20,10
	ldi R21,4
d1:       
	dec R20
	brne d1
	dec R21
	brne d1
	ret

Delay1:
	ldi R20,200
	ldi R21,200
d2:       
	dec R20
	brne d2
	dec R21
	brne d2
	ret
	
.eseg