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Код: Выделить всё

  TIM2->PSCR = 0;                         

  TIM2->CCMR1 |= TIM2_CCMR_CCxS_1;          // 10: CC1 channel is configured as input, IC1 is mapped on TI2FP1
  TIM2->CCMR2 |= TIM2_CCMR_CCxS_0;          // 01: CC2 channel is configured as input, IC2 is mapped on TI2FP2

  TIM2->CCER1 &= ~TIM2_CCER1_CC1P;          // 0: Capture is done on a rising edge of TI2F
  TIM2->CCER1 |= TIM2_CCER1_CC2P;           // 1: Capture is done on a falling edge of TI2F 

  TIM2->CR1 |= TIM2_CR1_URS;

  TIM2->CCER1 |= TIM2_CCER1_CC1E;           // Capture enabled
  TIM2->CCER1 |= TIM2_CCER1_CC2E;           // Capture enabled
  
  TIM2->IER |= TIM2_IER_CC1IE;
  TIM2->IER |= TIM2_IER_CC2IE;  
  TIM2->IER |= TIM2_IER_UIE;
  
  TIM2->CR1 |= TIM2_CR1_CEN;                    // Counter Enable 

Код: Выделить всё

 INTERRUPT_HANDLER(TIM2_UPD_OVF_BRK_IRQHandler, 13)
 {   
  cnt_ref_ovf++;
    
  TIM2->SR1 &= ~TIM2_SR1_UIF;         
 }


 INTERRUPT_HANDLER(TIM2_CAP_COM_IRQHandler, 14)
 {
  if(TIM2->SR1 & TIM2_SR1_CC1IF)
  {
   cnt_ref_ovf_CC1 = cnt_ref_ovf;
   
   TIM2->SR1 &= ~TIM2_SR1_CC1IF; 
  }

  if(TIM2->SR1 & TIM2_SR1_CC2IF)
  {
   cnt_ref_ovf_CC2 = cnt_ref_ovf;

   temp1  = (uint16_t)(TIM2->CCR1H) << 8;
   temp1 |= (cnt_ref_ovf_CC1 * 65536) | TIM2->CCR1L;
  
   temp2  = (uint16_t)(TIM2->CCR2H) << 8;
   temp2 |= (cnt_ref_ovf_CC2 * 65536) | TIM2->CCR2L;
  
   value = temp2 - temp1;

   TIM2->EGR |= TIM2_EGR_UG;                     // Update Event
   nop();
   nop();

   TIM2->SR1 = 0;

   cnt_ref_ovf = 0;
   cnt_ref_ovf_CC1 = 0;
   cnt_ref_ovf_CC2 = 0;    
  }
    
 }