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Код: Выделить всё

signal divider: std_logic_vector (24 downto 0) := (others=>'0');

process(clk)
begin
    if clk'event and clk='1' then
         divider <= divider+1;
         if divider = conv_std_logic_vector(25000000, 25) then
              divider<=(others=>'0');
         end if;
     end if;
end process;

out <= '1' when (divider > conv_std_logic_vector(12500000-1, 25)) else '0';

Код: Выделить всё

 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ANDE is
port (
   X1,X2 : in std_logic;
   Y :out std_logic
);
end ANDE;

architecture ANDA of ANDE is
begin
Y<=X1 and X2;
end ANDA;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity JFF is
port (
   J,C,R : in std_logic;
   Q : inout std_logic
);
end JFF;

architecture JK of JFF is
begin
process (C,R)
begin
   if R='1' then   
      Q <= '0';
   elsif (C'event and C='1') then 
      if J='1' then Q <= not Q;
		end if;
   end if;
end process;
end JK;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity divider is
generic (Nd : integer := 24);
    Port ( Clock : in std_logic;
          
           Clk_deb : out std_logic;
				 Clk_takt : out std_logic;
           reset : in std_logic);
end divider;

architecture Behavioral of divider is
component JFF
port ( J,C,R : in std_logic;
       Q : inout std_logic);
end component;
component ANDE is
port (
   X1,X2 : in std_logic;
   Y : out std_logic
);
end component;
signal T,V: std_logic_vector(0 to Nd);
begin
T(0)<='1';
 Clk_deb<=V(17);
Clk_takt<=V(25);


ST0: JFF port map(J=>T(0),C=>Clock,R=>reset,Q=>V(1));
JK1: for i in 1 to Nd-1 generate
     begin
  ST1: ANDE port map(X1=>T(i-1),X2=>V(i),Y=>T(i));
  ST2: JFF port map(J=>T(i),C=>Clock,R=>reset,Q=>V(i+1));
    end generate;
end Behavioral;

Код: Выделить всё

if (count>50000000) then                         
 clk<='0';     
      else	    
         clk<='1';
     end if;