КОД ОЗУ

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

entity ram is
generic(
width_adr :   integer:=12;
width_data : integer:=12;
depth : integer:=2**12
);
port(
DATA_IN : in std_logic_vector(width_data-1 downto 0);
ADR :in std_logic_vector(width_adr-1 downto 0);
CS :in std_logic;
WE : in std_logic;
DATA_OUT : out std_logic_vector(width_data-1 downto 0)
);
end ram;
architecture beh of ram is
type mem_ram is array(depth-1 downto 0) of std_logic_vector(width_data-1 downto 0);
--Signal ram_el : mem_ram;

begin
process(CS,WE)
variable address: natural;
variable ram_el : mem_ram;
begin
address:=to_integer(unsigned(ADR));
if(CS='1') then
if (WE='1') then
ram_el(address):=DATA_IN;
else DATA_OUT<=ram_el(address);
end if;
end if;
end process;
end beh;