static inline void gpio_setup(){
    // Enable clocks to the GPIO subsystems, turn on AFIO clocking to disable SWD/JTAG
    RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_AFIOEN;
    // turn off JTAG (PB3/4 is in use)
    AFIO->MAPR = AFIO_MAPR_SWJ_CFG_JTAGDISABLE;
    // turn off USB pullup
    USBPU_OFF();
    // Set led as opendrain output
    GPIOC->CRH = CRH(13, CNF_ODOUTPUT|MODE_SLOW);
    // SCREEN color PINs: PA0..PA5
    GPIOA->CRL = CRL(0, CNF_PPOUTPUT|MODE_FAST) | CRL(1, CNF_PPOUTPUT|MODE_FAST) | CRL(2, CNF_PPOUTPUT|MODE_FAST) |
                 CRL(3, CNF_PPOUTPUT|MODE_FAST) | CRL(4, CNF_PPOUTPUT|MODE_FAST) | CRL(5, CNF_PPOUTPUT|MODE_FAST);
    // USB pullup - opendrain output
    GPIOA->CRH = CRH(15, CNF_PPOUTPUT|MODE_SLOW);
    // A..D, LAT, nOE: PB4..PB9
    GPIOB->CRL = CRL(4, CNF_PPOUTPUT|MODE_FAST) | CRL(5, CNF_PPOUTPUT|MODE_FAST) | CRL(6, CNF_PPOUTPUT|MODE_FAST) | CRL(7, CNF_PPOUTPUT|MODE_FAST);
    GPIOB->CRH = CRH(8, CNF_PPOUTPUT|MODE_FAST) | CRH(9, CNF_PPOUTPUT|MODE_FAST);
}

static inline void tim_setup(){
    SET(nOE); // turn off output
    GPIOA->CRL |= CRL(6, CNF_AFPP|MODE_FAST);
    RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
    // 72MHz & 7ARR = 9MHz
    TIM3->PSC = 20000;
    TIM3->ARR = 7;
    TIM3->CCMR1 = TIM_CCMR1_OC1M; // PWM mode 2 (inactive->active)
    //TIM3->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1; // PWM mode 1 (active->inactive)
    TIM3->CCER = TIM_CCER_CC1E; // output 1 enable
    TIM3->DIER = TIM_DIER_UDE; // enable DMA requests
    RCC->AHBENR |= RCC_AHBENR_DMA1EN;
    // memsize 32bit, periphsize 32bit, memincr, mem2periph, full transfer interrupt
    DMA1_Channel3->CCR = DMA_CCR_PSIZE_1 | DMA_CCR_MSIZE_1 | DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE;
    DMA1_Channel3->CMAR = (uint32_t)dmabuf;
    DMA1_Channel3->CPAR = (uint32_t)&GPIOA->BSRR;
    NVIC_EnableIRQ(DMA1_Channel3_IRQn);
}

static uint8_t blknum_curr = 0;
void TIM_DMA_transfer(uint8_t blknum){
    TIM3->CR1 = 0; // turn off timer
    transfer_done = 0;
    COLR_port->BSRR = dmabuf[0];
    DMA1_Channel3->CNDTR = SCREEN_WIDTH;
    DMA1_Channel3->CCR |= DMA_CCR_EN; // start DMA
    TIM3->CCR1 = 4; // 50% PWM
    TIM3->CR1 = TIM_CR1_CEN; // turn on timer
    blknum_curr = blknum;
}

void dma1_channel3_isr(){
    TIM3->CR1 |= TIM_CR1_OPM; // set one pulse mode to turn off timer after last CLK pulse
    DMA1_Channel3->CCR &= ~DMA_CCR_EN; // stop DMA
    while(TIM3->CNT < 7);
    SET(nOE); // clear main output
    ADDR_port->ODR = (ADDR_port->ODR & ~(ADDR_pin)) | (blknum_curr << ADDR_roll); // set address
    SET(LAT); // activate latch
    DMA1->IFCR = DMA_IFCR_CGIF3;
    transfer_done = 1;
    CLEAR(LAT);
    CLEAR(nOE); // activate main output
}