А зачем открывать сам прожект то, достаточно только файлы с текстом программы прикрутить... вериложные или VHDL - левские... 
Код: Выделить всё
Warning (275008): Primitive "DFF" of instance "inst1" not used
Warning (275008): Primitive "NOT" of instance "inst2" not used
Warning (275008): Primitive "WIRE" of instance "inst7" not used
Warning (12125): Using design file signet_notsignet12.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info (12023): Found entity 1: signet_notsignet12
Info (12023): Found entity 1: signet_notsignet12
Warning (10631): VHDL Process Statement warning at CIC_Last_edition.vhd(137): inferring latch(es) for signal or variable "czi", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at CIC_Last_edition.vhd(137): inferring latch(es) for signal or variable "czq", which holds its previous value in one or more paths through the process
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "dac_r1[11]" is stuck at GND
Warning (13410): Pin "dac_r1[10]" is stuck at VCC
Warning (13410): Pin "dac_r1[9]" is stuck at VCC
Warning (13410): Pin "dac_r1[8]" is stuck at VCC
Warning (13410): Pin "dac_r1[7]" is stuck at VCC
Warning (13410): Pin "dac_r1[6]" is stuck at VCC
Warning (13410): Pin "dac_r1[5]" is stuck at VCC
Warning (13410): Pin "dac_r1[4]" is stuck at VCC
Warning (13410): Pin "dac_r1[3]" is stuck at VCC
Warning (13410): Pin "dac_r1[2]" is stuck at VCC
Warning (13410): Pin "dac_r1[1]" is stuck at VCC
Warning (13410): Pin "dac_r1[0]" is stuck at VCC
Warning (13410): Pin "dac_r2[11]" is stuck at GND
Warning (13410): Pin "dac_r2[10]" is stuck at VCC
Warning (13410): Pin "dac_r2[9]" is stuck at VCC
Warning (13410): Pin "dac_r2[8]" is stuck at VCC
Warning (13410): Pin "dac_r2[7]" is stuck at VCC
Warning (13410): Pin "dac_r2[6]" is stuck at VCC
Warning (13410): Pin "dac_r2[5]" is stuck at VCC
Warning (13410): Pin "dac_r2[4]" is stuck at VCC
Warning (13410): Pin "dac_r2[3]" is stuck at VCC
Warning (13410): Pin "dac_r2[2]" is stuck at VCC
Warning (13410): Pin "dac_r2[1]" is stuck at VCC
Warning (13410): Pin "dac_r2[0]" is stuck at VCC
Warning (20013): Ignored assignments for entity "SDR_TEST" -- entity does not exist in design
Warning (20014): Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity SDR_TEST -section_id "Root Region" was ignored
Warning (20014): Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity SDR_TEST -section_id "Root Region" was ignored
Warning (21074): Design contains 24 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "in_Q[11]"
Warning (15610): No output dependent on input pin "in_Q[10]"
Warning (15610): No output dependent on input pin "in_Q[9]"
Warning (15610): No output dependent on input pin "in_Q[8]"
Warning (15610): No output dependent on input pin "in_Q[7]"
Warning (15610): No output dependent on input pin "in_Q[6]"
Warning (15610): No output dependent on input pin "in_Q[5]"
Warning (15610): No output dependent on input pin "in_Q[4]"
Warning (15610): No output dependent on input pin "in_Q[3]"
Warning (15610): No output dependent on input pin "in_Q[2]"
Warning (15610): No output dependent on input pin "in_Q[1]"
Warning (15610): No output dependent on input pin "in_Q[0]"
Warning (15610): No output dependent on input pin "in_I[11]"
Warning (15610): No output dependent on input pin "in_I[10]"
Warning (15610): No output dependent on input pin "in_I[9]"
Warning (15610): No output dependent on input pin "in_I[8]"
Warning (15610): No output dependent on input pin "in_I[7]"
Warning (15610): No output dependent on input pin "in_I[6]"
Warning (15610): No output dependent on input pin "in_I[5]"
Warning (15610): No output dependent on input pin "in_I[4]"
Warning (15610): No output dependent on input pin "in_I[3]"
Warning (15610): No output dependent on input pin "in_I[2]"
Warning (15610): No output dependent on input pin "in_I[1]"
Warning (15610): No output dependent on input pin "in_I[0]"
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Warning (169177): 25 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
Info (169178): Pin in_Q[11] uses I/O standard 3.3-V LVTTL at 31
Info (169178): Pin in_Q[10] uses I/O standard 3.3-V LVTTL at 32
Info (169178): Pin in_Q[9] uses I/O standard 3.3-V LVTTL at 33
Info (169178): Pin in_Q[8] uses I/O standard 3.3-V LVTTL at 39
Info (169178): Pin in_Q[7] uses I/O standard 3.3-V LVTTL at 46
Info (169178): Pin in_Q[6] uses I/O standard 3.3-V LVTTL at 49
Info (169178): Pin in_Q[5] uses I/O standard 3.3-V LVTTL at 50
Info (169178): Pin in_Q[4] uses I/O standard 3.3-V LVTTL at 51
Info (169178): Pin in_Q[3] uses I/O standard 3.3-V LVTTL at 52
Info (169178): Pin in_Q[2] uses I/O standard 3.3-V LVTTL at 53
Info (169178): Pin in_Q[1] uses I/O standard 3.3-V LVTTL at 54
Info (169178): Pin in_Q[0] uses I/O standard 3.3-V LVTTL at 55
Info (169178): Pin in_I[11] uses I/O standard 3.3-V LVTTL at 59
Info (169178): Pin in_I[10] uses I/O standard 3.3-V LVTTL at 60
Info (169178): Pin in_I[9] uses I/O standard 3.3-V LVTTL at 64
Info (169178): Pin in_I[8] uses I/O standard 3.3-V LVTTL at 65
Info (169178): Pin in_I[7] uses I/O standard 3.3-V LVTTL at 66
Info (169178): Pin in_I[6] uses I/O standard 3.3-V LVTTL at 67
Info (169178): Pin in_I[5] uses I/O standard 3.3-V LVTTL at 68
Info (169178): Pin in_I[4] uses I/O standard 3.3-V LVTTL at 69
Info (169178): Pin in_I[3] uses I/O standard 3.3-V LVTTL at 76
Info (169178): Pin in_I[2] uses I/O standard 3.3-V LVTTL at 77
Info (169178): Pin in_I[1] uses I/O standard 3.3-V LVTTL at 79
Info (169178): Pin in_I[0] uses I/O standard 3.3-V LVTTL at 80
Info (169178): Pin CLK uses I/O standard 3.3-V LVTTL at 25
Warning (20013): Ignored assignments for entity "SDR_TEST" -- entity does not exist in design
Warning (20014): Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity SDR_TEST -section_id "Root Region" was ignored
Warning (20014): Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity SDR_TEST -section_id "Root Region" was ignored
Warning (20014): Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity SDR_TEST -section_id "Root Region" was ignored
Warning (20014): Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity SDR_TEST -section_id "Root Region" was ignored
Код: Выделить всё
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:33:57 01/26/2012
-- Design Name:
-- Module Name: CIC_Last_edition - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CIC_Last_edition is
generic (dec : integer := 16;
din : integer := 12;
dout : integer := 12
);
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
CE : in STD_LOGIC;
DI : in STD_LOGIC_VECTOR (din - 1 downto 0);
DQ : in STD_LOGIC_VECTOR (din - 1 downto 0);
R : in STD_LOGIC_VECTOR (dec - 1 downto 0);
QI : out STD_LOGIC_VECTOR (dout - 1 downto 0);
QQ : out STD_LOGIC_VECTOR (dout - 1 downto 0);
CV : out std_logic
);
end CIC_Last_edition;
architecture Behavioral of CIC_Last_edition is
SIGNAL ii : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL iq : STD_LOGIC_VECTOR (11 DOWNTO 0);
begin
ii <= DI;
iq <= DI;
integr: process(CLK, RESET, CE)
begin
if RESET = '0' then
QI <= ii;
QQ <= iq;
else
QI <= "000000000001";
QQ <= "000000000001";
end if;
end process integr;
END Behavioral;Код: Выделить всё
Warning (10631): VHDL Process Statement warning at CIC_Last_edition.vhd(137): inferring latch(es) for signal or variable "czi", which holds its previous value in one or more paths through the processнет так и не удалось запуститьДа кстати, как там проект то, запустился?