Код: Выделить всё
.macro clrb
cbr @0,1<<@1
.endmacro
.macro setb
sbr @0,1<<@1
.endmacro
.macro sfbs
lds r16,@0
sbrs r16,@1
.endmacro
.macro sfbc
lds r16,@0
sbrc r16,@1
.endmacro
.macro stfb
lds r16,@0
sbr r16,@1
sts @0,r16
.endmacro
.macro clfb
lds r16,@0
cbr r16,@1
sts @0,r16
.endmacro
.macro ldiw
ldi @0,High(@2)
ldi @1,Low(@2)
.endmacro
.macro ldx
ldi XH,High(@0)
ldi XL,Low(@0)
.endmacro
.macro ldy
ldi YH,High(@0)
ldi YL,Low(@0)
.endmacro
.macro ldz
ldi ZH,High(@0)
ldi ZL,Low(@0)
.endmacro
.macro pushx
push XL
push XH
.endmacro
.macro pushy
push YL
push YH
.endmacro
.macro pushz
push ZL
push ZH
.endmacro
.macro popx
pop XH
pop XL
.endmacro
.macro popy
pop YH
pop YL
.endmacro
.macro popz
pop ZH
pop ZL
.endmacro
.macro stsi
ldi r16,@1
sts @0,r16
.endmacro
.macro stsiw
ldi r16,high(@1)
sts @0+1,r16
ldi r16,low(@1)
sts @0,r16
.endmacro
.macro outi
ldi r16,@1
out @0,r16
.endmacro
.macro outiw
ldi r16,high(@1)
out @0H,r16
ldi r16,low(@1)
out @0L,r16
.endmacro
.macro adi
subi @0,-@1
.endmacro
.macro adci
sbci @0,-@1
.endmacro
.macro addiw
subi @0L,LOW(-@1)
sbci @0H,HIGH(-@1)
.endmacro
.macro cpw
cp @0,@1
cpc @2,@3
.endmacro
.macro subiw
subi @0L,LOW(@1)
sbci @0H,HIGH(@1)
.endmacro
.macro addw
add @0L,@1
adc @0H,@2
.endmacro
.macro shiftlwz
lsl ZL
rol ZH
.endmacro
.macro shiftrw
lsr @0H
ror @0L
.endmacro
.macro INIT_STACK
.ifdef SPH
outi SPH,HIGH(RAMEND)
.endif
outi SPL,LOW(RAMEND)
.endmacro
.macro INIT_WATCH_DOG
outi WDTCR,1<<WDTOE | 1<<WDE ; | 1<<WDP2 | 1<<WDP1 | 1<<WDP0
.endmacro
.macro INIT_SLEEP_MODE
in r16,MCUCR
sbr r16,1<<SE
out MCUCR,Temp
.endmacro
.macro INIT_EXT_INT0
in r16,MCUCR
sbr r16,1<<ISC00 | 1<<ISC01
out MCUCR,Temp
in r16,GICR
sbr r16,1<<INT0
out GICR,r16
.endmacro
.macro INIT_EXT_INT1
in r16,MCUCR
sbr r16,1<<ISC10 | 1<<ISC11
out MCUCR,Temp
in r16,GICR
sbr r16,1<<INT1
out GICR,r16
.endmacro
.macro INIT_EXT_INT2
in r16,MCUCR
sbr r16,1<<SE
out MCUCR,Temp
in r16,MCUCSR
sbr r16,1<<ISC2
out MCUCSR,Temp
in r16,GICR
sbr r16,1<<INT2
out GICR,r16
.endmacro
.macro INIT_TIMER0
out TCNT0,RCLR
in r16,TIMSK
sbr r16,1<<OCIE0
out TIMSK,r16
outi OCR0,(XTAL/64/1000)
outi TCCR0,1<<CS00 | 1<<CS01
.endmacro
.macro INIT_TIMER1
in r16,TIMSK
sbr r16,1<<OCIE1A
out TIMSK,r16
out TCNT1H,Zero
out TCNT1L,Zero
ldi r16,High(36)
out OCR1AH,r16
ldi r16,Low(36)
out OCR1AL,r16 ; При частоте кварца 7,3728 Мгц число 72=10 мс.
ldi r16,0x05
out TCCR1B,r16
.endmacro
.macro INIT_TIMER2
out TCNT2,RCLR
in r16,TIMSK
sbr r16,1<<OCIE2
out TIMSK,r16
outi OCR2,(XTAL/64/1000)
outi TCCR2,4
.endmacro
.macro Case
cpi STREG,@0
brne Exit_Case
rjmp @1
Exit_Case:
.endmacro
.macro Case_Not_Equal
cpi STREG,@0
breq Exit_Case
rjmp @1
Exit_Case:
.endmacro
.macro Read_State
lds r16,@0
.endmacro
.macro Set_State
ldi r16,@1
sts @0,r16
.endmacro
.macro Set_Mode
ldi r16,@1
sts @0,r16
.endmacro
.macro Check_States
cpi r16,@0
brlo Check_States_Exit
rjmp @1
Check_States_Exit:
.endmacro
.macro Read_Last_State
lds r17,@0
.endmacro
.macro ClearRegisters
clr r0
clr r1
clr r2
clr r3
clr r4
clr r5
clr r6
clr r7
clr r8
clr r9
clr r10
clr r11
clr r12
clr r13
clr r14
clr r15
clr r16
clr r17
clr r18
clr r19
clr r20
clr r21
clr r22
clr r23
clr r24
clr r25
clr r26
clr r27
clr r28
clr r29
clr r30
clr r31
.endmacro
.macro Set_State
ldi FSM_STATE, @0
.endmacro
.macro Clear_Registers
clr ZH
ldi ZL, 30
Clear_Register_Cycle:
dec ZL
st Z, ZH
brne Clear_Register_Cycle
.endmacro
;*************************************************************************
;=========== SRAM ====================
;*************************************************************************
.macro OUT_SRAM
ldi XH,HIGH(@0)
ldi XL,LOW(@0)
ldi Data_H,HIGH(@1)
ldi Data_L,LOW(@1)
rcall _OUT_SRAM
.endmacro
.macro OUTI_SRAM
ldi XH,HIGH(@0)
ldi XL,LOW(@0)
ldi r17,@1
ldi r16,@2
rcall _OUT_SRAM
.endmacro
_OUT_SRAM:
st X+,r16
dec r17
brne _OUT_SRAM
ret
.macro Copy_SRAM
.if @3==YES
push YH
push YL
.endif
ldi XH,HIGH(@0)
ldi XL,LOW(@0)
ldi YH,HIGH(@1)
ldi YL,LOW(@1)
ldi r17,@2
rcall _Copy_SRAM
.if @3==YES
pop YL
pop YH
.endif
.endmacro
_Copy_SRAM:
ld r16,X+
st Y+,r16
dec r17
brne _Copy_SRAM
ret
.macro Clear_SRAM
ldx SRAM_START
Clear_SRAM_Cycle:
st X+,RCLR
cpi XL,LOW(SRAM_START+SRAM_SIZE)
brne Clear_SRAM_Cycle
cpi XH,HIGH(SRAM_START+SRAM_SIZE)
brne Clear_SRAM_Cycle
.endmacro
;*************************************************************************
;*************************************************************************
;========== EEPROM ===================
;*************************************************************************
;Так как возможна случайная запись в EEPROM в случае сбоя питания, то:
;1 - В микроконтроллере включить контроль снижения напряжения питания.
;2 - Первый (0x00) байт никогда не используется.
;3 - После ресета обнулить указатель адреса EEPROM.
;Решения для увеличения ресурса EEPROM:
;4 - Перед записью считывается байт, предназначенный для записи,
;проверяется на равенство с записываемым, если байты равны, то переход
;к записи следующего байта.
;5 - В конце работы с EEPROM обнулить указатель адреса.
#if (EEPROM==YES)
.macro Read_EEPROM
ldix @0 ; Указатель адреса EEPROM.
ldiy @1 ; Указатель адреса SRAM.
ldi r17,@2
rcall _Read_EEPROM
.endmacro
_Read_EEPROM:
sbic EECR,EEWE
rjmp _Read_EEPROM
.ifdef EEARH
out EEARH,XH
.endif
out EEARL,XL
sbi EECR,EERE
sbi EECR,EERE
in EEDREG,EEDR
st Y+,EEDREG
adiw XL,1
dec r17
brne _Read_EEPROM
_Read_EEPROM_0:
sbic EECR,EEWE
rjmp _Read_EEPROM_0
.ifdef EEARH
out EEARH,RCLR
.endif
out EEARL,RCLR
ret
EERead:
sbic EECR,EEWE
rjmp EERead
.ifdef EEARH
out EEARH,XH
.endif
out EEARL,XL
sbi EECR,EERE
sbi EECR,EERE
in EEDREG,EEDR
EERead_1:
sbic EECR,EEWE
rjmp EERead_1
.ifdef EEARH
out EEARH,RCLR
.endif
out EEARL,RCLR
ret
EEWrite:
sbic EECR,EEWE
rjmp EEWrite
.ifdef EEARH
out EEARH,XH
.endif
out EEARL,XL
out EEDR,EEDREG
sbi EECR,EEMWE
sbi EECR,EEWE
EEWrite_1:
sbic EECR,EEWE
rjmp EEWrite_1
.ifdef EEARH
out EEARH,RCLR
.endif
out EEARL,RCLR
ret
.macro Write_EEPROM
ldiy @0 ; Указатель адреса SRAM.
ldix @1 ; Указатель адреса EEPROM.
ldi r17,@2
rcall _Write_EEPROM
.endmacro
_Write_EEPROM:
sbic EECR,EEWE
rjmp _Write_EEPROM
.ifdef EEARH
out EEARH,XH
.endif
out EEARL,XL
ld EEDREG,Y+
out EEDR,EEDREG
sbi EECR,EEMWE
sbi EECR,EEWE
adiw XL,1
dec r17
brne _Write_EEPROM
_Write_EEPROM_0:
sbic EECR,EEWE
rjmp _Write_EEPROM_0
.ifdef EEARH
out EEARH,RCLR
.endif
out EEARL,RCLR
ret
.macro Clear_EEPROM
ldx @0
ldy @1
rcall _Clear_EEPROM
.endmacro
_Clear_EEPROM:
sbic EECR,EEWE
rjmp _Clear_EEPROM
.ifdef EEARH
out EEARH,XH
.endif
out EEARL,XL
out EEDR,RCLR
sbi EECR,EEMWE
sbi EECR,EEWE
adiw XL,1
sbiw YL,1
brne _Clear_EEPROM
_Clear_EEPROM_0:
sbic EECR,EEWE
rjmp _Clear_EEPROM_0
.ifdef EEARH
out EEARH,RCLR
.endif
out EEARL,RCLR
ret
#endif
;*************************************************************************
/************************************************************************/
#if (BCD==YES)
.dseg
HEX_DEC_BUFFER:
.equ HEX_DEC_BUFFER_LENGHT = 5
.byte HEX_DEC_BUFFER_LENGHT
.cseg
Hex_Dec:
ldx HEX_DEC_BUFFER
ldi r17,HIGH(10000)
ldi r16,LOW(10000)
rcall Digit
st X+,r18
ldi r17,HIGH(1000)
ldi r16,LOW(1000)
rcall Digit
st X+,r18
ldi r17,HIGH(100)
ldi r16,LOW(100)
rcall Digit
st X+,r18
ldi r17,HIGH(10)
ldi r16,LOW(10)
rcall Digit
st X+,r18
mov r16,r14
ori r16,0x30
st X+,r16
Hex_Dec_End:
ret
Digit:
ldi r18,-1
Digit_Cycle:
inc r18
sub r14,r16
sbc r15,r17
brsh Digit_Cycle
add r14,r16
adc r15,r17
ori r18,0x30
ret
#endif
/************************************************************************/
/************************************************************************/
Empty_Action:
ret
/************************************************************************/
/************************************************************************/
Table_Bits:
.db 0b00000001, 0b00000010, 0b00000100, 0b00001000
.db 0b00010000, 0b00100000, 0b01000000, 0b10000000
/************************************************************************/
/************************************************************************/
.macro end_array
.db 0xFF,0xFF
.endmacro
/************************************************************************/