Который потом удаётся снять только в stvp
От чего так?

А вы два раза читаете sr3, может в этом дело?EV6:ADDR=1, cleared by reading SR1 register followed by reading SR3.
А вы два раза читаете sr3, может в этом дело?[/uquote]EV6:ADDR=1, cleared by reading SR1 register followed by reading SR3.
Для пробы, может поставить тупые паузы между каждым EVn?Due to timing constraints, when in standard mode if CCR is less than 9 (i.e. with peripheral clock below 2 MHz) with
f
MASTER = fCPUand the event interrupt disabled, the following procedure must be followed:
modify the reset sequence in order to insert at least 5 cycles between each operations in the flag clearing sequence. For
example, when fMASTER = fCPU= 1 MHz, use the following sequence to poll the SB bit:
_label_wait: BTJF I2C_SR1,SB,_label_wait
NOP ;
NOP;
NOP ;
NOP
NOP
LD I2C_DR, A ; once executed, the SB bit is then cleared.