немного не по верилогу! Написал прошивку в итоге)
module test1(OUT,WR,RESET,RD,CS,DAT,A,D);
input wire [3:0] A;
input wire WR, RD, CS, RESET;
output wire [7:0] D;
inout [7:0] DAT;
inout [8:1] OUT;
reg [7:0] D_reg;
reg [8:1] INREG;
always @(negedge WR or negedge RESET)
begin
if (RESET == 0)
INREG <= 0;
else if (!CS && A ==
INREG <= DAT;
end
assign DAT[7:0]=(!CS&!RD)?D[7:0]:8'bz;
assign OUT[8:1]=(INREG[8:1])?0:8'bz;
assign D = D_reg;
always @(*)
case (A[3:0])
0: D_reg = 8'd32;
1: D_reg = 8'd28;
2: D_reg = 8'd8;
3: D_reg = 8'd8;
8: D_reg = INREG[8:1];
default: D_reg = 0;
endcase
endmodule
Как для нее теперь симмуляцию написать?
//-----------------------------------------------------------------------------
//
// Title : test1_tb
// Design : 44pin
// Author :
// Company :
//
//-----------------------------------------------------------------------------
//
// File : test1_TB.v
// Generated : Tue Oct 2 16:37:19 2012
// From : c:\My_Designs\EPM3064\44pin\src\TestBench\test1_TB_settings.txt
// By : tb_verilog.pl ver. ver 1.2s
//
//-----------------------------------------------------------------------------
//
// Description :
//
//-----------------------------------------------------------------------------
`timescale 1ns / 1ps
module test1_tb;
//Internal signals declarations:
tri [8:1]OUT_bidir;
reg [8:1]OUT;
//Continous assignment for inout port "OUT".
assign OUT_bidir = OUT;
reg WR;
reg RESET;
reg RD;
reg CS;
tri [7:0]DAT_bidir;
reg [7:0]DAT;
//Continous assignment for inout port "DAT".
assign DAT_bidir = DAT;
reg [3:0]A;
wire [7:0]D;
// Unit Under Test port map
test1 UUT (
.OUT(OUT_bidir),
.WR(WR),
.RESET(RESET),
.RD(RD),
.CS(CS),
.DAT(DAT_bidir),
.A(A),
.D(D));
initial
begin
RESET=1'b0;
WR=1'b0;
RD=1'b0;
CS=1'b0;
DAT[7:0]=1'b0;
A[3:0]=1'b0;
#300 RESET=1'b1;
#300 WR=1'b1;
#300 RD=1'b1;
#300 CS=1'b1;
#300 DAT[7:0]=1'b1;
#300 A[3:0]=1'b1;
end
always #30 WR=~WR;
endmodule
не хочет с такой работать...
